Gapper-PLL Frequency Synthesis for Output Frequencies Above Input
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Solution Overview
Problem
Conventional gapper-based frequency synthesizers are limited to applications requiring a frequency ratio greater than 1, as they cannot generate output signals with higher frequencies than the input signal, which is disadvantageous in scenarios like converting a 622.08 MHz clock to a 669.326 MHz clock.
Innovation Solution
A frequency synthesizer configuration that includes a gapper and a first integer divider, allowing the gapper to borrow a factor from the divider to generate a rational divide ratio greater than 1, enabling the generation of output signals with higher frequencies by incorporating a PLL to attenuate jitter and achieve the desired frequency ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a gapper is used to generate a gapped signal with divide ratio G>=1, then the average frequency of the gapped signal is lower than the input signal, but the synthesizer cannot generate output signals with higher frequencies than the input signal
Solution Approach 1:
The frequency synthesis process is segmented into multiple stages: a gapper stage that generates a gapped signal with divide ratio G, and a subsequent integer divider stage with divide ratio N. This segmentation allows the overall divide ratio D to be expressed as D = G × N, where G >= 1 and N can be less than 1 when borrowing is applied. The segmentation enables flexible frequency ratio selection while maintaining a systematic architecture.
Solution Approach 2:
The system dynamically adjusts the divide ratio G of the gapper based on the desired output frequency. When the target frequency ratio requires D < 1, the system borrows from the integer divider to make G > 1, and compensates by adjusting N accordingly. This dynamic adjustment allows the synthesizer to adapt to different frequency conversion scenarios, including both frequency multiplication and division.
2Ease of operation
If the gapper incorporates a factor greater than 1 from the integer divider, then the gapper can perform division by G > 1, but the integer divider must operate with a reduced divide ratio
Solution Approach 1:
The system employs a phase-locked loop (PLL) that provides feedback to maintain frequency accuracy. The PLL locks onto the output frequency and adjusts the control signals to ensure that the combined effect of the gapper and integer divider produces the exact desired frequency ratio. This feedback mechanism compensates for any inaccuracies introduced by the dynamic adjustment of divide ratios.
Solution Approach 2:
The system changes the operating parameters (divide ratios G and N) based on the desired frequency conversion. By dynamically selecting different values for G and N, the system can achieve various frequency ratios while maintaining accuracy through the PLL's phase and frequency detection capabilities. The parameters are adjusted in a coordinated manner to preserve the overall frequency relationship.
Data Source
AI summary
Systems and methods for frequency synthesis using a gapper. A frequency synthesizer may comprise a gapper, a first integer divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the first integer divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a gapped signal output from the first integer divider and attenuating jitter from the gapped signal.