Garbled Circuit Slicing for Memory-Limited Secure Computation
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Solution Overview
Problem
Garble-and-evaluate techniques for Boolean circuits are memory-intensive, making them challenging to execute in memory-limited environments, such as trusted execution environments (TEEs), where they are needed for secure data processing and authentication.
Innovation Solution
The method involves initializing auxiliary garbling data for the entire circuit, generating and transmitting circuit slices for update and finalization functions, and garbling these slices in a memory-limited environment, allowing for secure computation without requiring all slices to be received by the evaluator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional garble-and-evaluate techniques are used for Boolean circuits, then cryptographic security is achieved, but memory requirements increase dramatically (more than two orders of magnitude greater than non-garbled evaluation)
Solution Approach 1:
The patent divides the Boolean circuit into multiple slices, where each slice represents a subset of the circuit gates. This segmentation allows the garbling process to be performed incrementally on smaller circuit portions rather than requiring all circuit data to be loaded into memory simultaneously, thereby reducing peak memory requirements while maintaining the cryptographic security of the garble-and-evaluate protocol.
Solution Approach 2:
The patent performs preliminary garbling of circuit slices before the actual evaluation phase. By pre-processing and garbling circuit slices in advance, the system can store only the essential garbled data structures in memory during evaluation, rather than requiring all intermediate computation data to be simultaneously available, thus reducing memory requirements while preserving security.
2Quantity of substance
If circuit slicing is implemented to reduce memory usage, then memory requirements decrease, but the complexity of the garbling process increases
Solution Approach 1:
The circuit is divided into slices that can be processed independently, allowing the garbling process to handle smaller, manageable portions at a time. This segmentation reduces the memory burden while the modular nature of slice processing helps manage complexity through systematic organization of the garbling operations.
Solution Approach 2:
The garbling process is performed periodically on successive circuit slices rather than attempting to garble the entire circuit at once. This periodic approach breaks down the complex task into repeated, simpler operations that can be executed in sequence, reducing overall process complexity while achieving the memory reduction goal.
Data Source
AI summary
Arrangements for use in garbling a circuit in a memory-limited environment, comprising: initializing auxiliary garbling data comprising a plurality of data features associated with execution of garbling operations for the entirety of the circuit being. initializing a plurality of input gates and a plurality of state gates; generating a circuit slice for an update function; setting the plurality of state gates as a plurality of new output-state-gates; generating a circuit slice for a finalization function, wherein the finalization function represented by a sub-circuit, the outputs of which are terminal gates; garbling the circuit slice generated for the finalization function to create a garbled circuit slice; and transmitting the garbled circuit slice substantially no later than completion of its creation; wherein initializing auxiliary garbling data is performed only once for the circuit and prior to initializing the plurality of input gates and the plurality of state gates.