Garbled Circuit White-Box Implementation for AES Key Protection

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Solution Overview

Problem

Current white-box implementations of cryptographic functions face practical limitations due to the size of lookup tables required, especially for symmetric block-ciphers like AES, which hinder their ideal security in protecting secret keys from disclosure.

Innovation Solution

The method involves producing a logic circuit implementing a cryptographic function using garbled circuits, where each wire is assigned two garbled values, and providing a garbled logic circuit to a second party for evaluation, embedding or inputting a cryptographic key, and using external encodings to enhance security without revealing intermediate computations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a huge lookup table is used to implement a white-box cryptographic function, then security against key disclosure is improved, but the implementation size and complexity become impractically large

Engineering Contradiction:
Improvesecurity against key disclosureVSAvoidimplementation size
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The cryptographic function is divided into multiple logic gates organized in a circuit structure. Each gate processes a portion of the cryptographic computation, breaking down the monolithic lookup table into manageable segments that can be evaluated sequentially, thereby reducing overall implementation complexity while maintaining security.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Garbled values serve as intermediaries between the plaintext input and the secret key. Instead of directly accessing the key through a large lookup table, the system uses garbled circuit evaluation where intermediate garbled values are computed and passed through the circuit, hiding the actual key values and reducing the need for massive pre-computed tables.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If random encodings are applied to lookup tables to introduce ambiguity, then security is improved, but the complexity of the implementation increases

Engineering Contradiction:
ImprovesecurityVSAvoidimplementation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system changes the parameter representation by using garbled values instead of direct key values. Each wire in the circuit carries garbled values that are randomly encoded versions of the actual logical values. This parameter transformation provides security through randomness while the structured circuit evaluation process keeps the implementation complexity manageable compared to fully randomized lookup tables.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If external encodings are used to replace encryption functions, then security against malicious adversaries is improved, but the evaluation time and computational overhead increase

Engineering Contradiction:
Improvesecurity against malicious adversariesVSAvoidevaluation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The garbled circuit is prepared in advance by the first party, including all the garbled values and circuit structure. This preliminary action allows the second party to simply evaluate the pre-prepared circuit without performing complex encoding operations during the actual cryptographic operation, thereby reducing evaluation time while maintaining security against malicious adversaries.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3413502B1White-box implementations with garbled circuits
Publication Date: 2020.07.08 NXP BV
  • EP3413502B1 patent drawingFigure 1~2
  • EP3413502B1 patent drawing
  • EP3413502B1 patent drawing

AI summary

A method for producing a white-box implementation of a cryptographic function using garbled circuits, including: producing, by a first party, a logic circuit implementing the cryptographic function using a plurality of logic gates and a plurality of wires; garbling the produced logic circuit, by the first party, including garbling the plurality of logic gates and assigning two garbled values for each of the plurality of wires; and providing a second party the garbled logic circuit and a first garbled circuit input value.