Gasket Buffer Management for Read Stacking in Data Processors

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Solution Overview

Problem

Data processing devices face challenges in managing buffered access requests, leading to increased latency and reduced data transfer bandwidth due to the consumption of integrated circuit area by large buffers and the need for redesigning interfaces to accommodate more read access requests.

Innovation Solution

The implementation of a protocol translation module (gasket) that controls the number of storage locations in buffers for read and write access requests, allowing more read access requests to be stored without increasing buffer size, and includes mechanisms for reissuing read access requests until inbound buffer space is available, optimizing data transfer bandwidth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If large buffers are used at the interface to improve communication bandwidth, then communication bandwidth is improved, but integrated circuit area consumption increases

Engineering Contradiction:
Improvecommunication bandwidthVSAvoidintegrated circuit area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent segments the buffer into two distinct parts: an outbound buffer for storing access requests and an inbound buffer for storing response information. This segmentation allows independent management of each buffer's size and timing characteristics, enabling the system to achieve high communication bandwidth without requiring a single large buffer that would consume excessive integrated circuit area.

Inventive Principle:
Principle #1Segmentation

2Productivity

If buffering of access requests is increased to improve communication bandwidth, then communication bandwidth is improved, but latency at the interconnect increases

Engineering Contradiction:
Improvecommunication bandwidthVSAvoidlatency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements dynamic control of buffer storage locations through threshold values. The number of buffer locations allocated to outbound and inbound buffers is not fixed but dynamically adjusted based on operational conditions and threshold comparisons. This dynamic allocation optimizes the balance between buffering capacity and latency, allowing the system to maintain high communication bandwidth while minimizing unnecessary buffering delays.

Inventive Principle:
Principle #15Dynamics

3Quantity of substance

If the number of storage locations for read access requests is increased to store more requests, then more read access requests can be stored, but buffer size must be increased

Engineering Contradiction:
Improvenumber of read access requests storedVSAvoidbuffer size
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent applies local quality by assigning different timing characteristics and management strategies to different parts of the buffer system. The outbound buffer for read access requests operates with different timing parameters than the inbound buffer for response information. This allows the system to store more read access requests in the outbound buffer without proportionally increasing the total buffer size, as each region is optimized for its specific function and timing requirements.

Inventive Principle:
Principle #3Local quality

4Quantity of substance

If interface redesign is performed to accommodate more read access requests, then more read access requests can be stored, but device complexity increases

Engineering Contradiction:
Improvenumber of read access requests storedVSAvoidinterface complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent avoids interface redesign by changing operational parameters instead of structural configuration. By adjusting threshold values and timing parameters, the system can accommodate more read access requests without modifying the interface architecture. This parameter-based approach maintains device complexity at acceptable levels while achieving the goal of storing more access requests.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8775699B2Read stacking for data processor interface
Publication Date: 2014.07.08 NXP USA INC
  • US8775699B2 patent drawing
  • US8775699B2 patent drawing
  • US8775699B2 patent drawing

AI summary

A gasket of a data processing device controls the number of released storage locations of a buffer where read and write access requests are stored so that more read access requests can be stored without a corresponding increase in the amount of space at the buffer to store write access requests. An interface of the gasket accepts new access requests from one or more requesting modules only when a number of released storage locations at a buffer associated with the interface (referred to as an outbound buffer) is above a threshold number. As long as the number of stored access requests at the outbound buffer are less than a threshold amount, a buffer location can be immediately released. In addition, the gasket is configured to issue read access requests from the outbound buffer without regard to whether the inbound buffer has space available.