GAT Block Allocation Across Memory Planes for Faster Address Resolution
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Solution Overview
Problem
Conventional methods for handling multiple host commands in memory systems result in decreased speed and IOPS due to inefficient management of host locations and metadata, leading to increased processing time.
Innovation Solution
The implementation of a data storage device with separate regions for data and metadata storage, utilizing asynchronous independent plane reads (AIPR) to parallelize command execution and manage metadata across different memory planes or metaplanes, enhancing parallel processing capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional methods are used to handle multiple host commands by sequentially resolving all host locations before issuing data sense commands, then command execution can be completed, but the overall speed and IOPS of the memory system decrease
Solution Approach 1:
The patent divides the GAT table into multiple segments stored in different memory planes (first GAT segment in first plane, second GAT segment in second plane). This segmentation allows parallel access to different portions of the GAT table simultaneously, enabling multiple host commands to be resolved in parallel rather than sequentially, thereby improving IOPS and reducing address resolution time.
Solution Approach 2:
The patent utilizes the plane dimension in 3D NAND memory to store different GAT segments in different planes. By transitioning from a single-plane sequential access model to a multi-plane parallel access model, the system can resolve multiple host commands simultaneously across different planes, significantly improving throughput and reducing latency.
2Speed
If a single open control block is maintained for all metadata, then device complexity is reduced, but the speed at which host locations are resolved decreases
Solution Approach 1:
The patent segments the control block into multiple open control blocks (first open control block for first metadata, second open control block for second metadata), each associated with different memory planes. This allows parallel metadata management and host command resolution across different planes, improving speed while distributing the complexity across multiple specialized control blocks rather than one monolithic block.
Solution Approach 2:
Each open control block is designed to handle multiple functions: managing metadata for specific planes, resolving host commands for those planes, and coordinating with corresponding GAT segments. This multi-functionality allows the system to improve resolution speed through parallelism while keeping each control block's design relatively simple and reusable across different planes.
Data Source
AI summary
A data storage device with efficient page table block allocation. In one example, a memory includes a plurality of memory dies. A controller is configured to allocate a first region of the memory for storing data received from an external electronic device, and allocate a second region of the memory for storing metadata associated with the data. The first region includes a first memory die of the plurality of memory dies, and the second region includes a second memory die of the plurality of memory dies different from the first memory die. The controller is further configured to receive, from the external electronic device, a write command including first data to be written to the memory, control the memory to write the first data to the first region, generate first metadata associated with the first data, and control the memory to write the first metadata to the second region.