Global Address Table Segmentation for Unaligned Flash Writes
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Solution Overview
Problem
Existing memory controllers face inefficiencies and data corruption risks during unaligned writes in non-volatile memory systems, as they require pre- and post-padding, increasing write amplification and overhead.
Innovation Solution
The Global Address Table (GAT) is modified to index data at an unaligned sector level, incorporating an aligned GAT Page for each Flash Management Unit (FMU) and an unaligned GAT Page for each sector, allowing unaligned writes without the need for pre- and post-padding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If pre- and post-padding is used to handle unaligned writes, then data alignment requirements are met, but write amplification and overhead increase
Solution Approach 1:
The Global Address Table is divided into multiple pages, with specific pages designated for aligned and unaligned writes. This segmentation allows the system to handle unaligned writes directly without requiring padding operations, as each GAT page can independently manage its own alignment requirements.
Solution Approach 2:
The system dynamically selects which GAT page to use based on whether the write operation is aligned or unaligned. This dynamic approach allows the memory controller to adapt to different write patterns without imposing fixed alignment requirements, thereby eliminating the need for pre- and post-padding operations.
2Manufacturing precision
If pre- and post-padding is performed for unaligned writes, then data is properly aligned to minimum write units, but data corruption risk increases
Solution Approach 1:
By segmenting the GAT into multiple pages with different alignment characteristics, the system isolates unaligned write operations to specific pages. This prevents padding operations from interfering with other data, thereby reducing the risk of data corruption while maintaining proper alignment where needed.
Solution Approach 2:
The unaligned GAT page acts as an intermediary structure that handles unaligned writes without requiring padding. This intermediary layer absorbs the alignment mismatch between host writes and memory requirements, preventing the need to read and manipulate existing data pages, thus eliminating data corruption risks.
3Measurement precision
If the GAT is loaded to cache for every unaligned write, then address mapping is accurate, but overhead increases
Solution Approach 1:
The GAT is segmented into multiple pages that can be independently cached. When an unaligned write occurs, the system only loads the specific unaligned GAT page into cache rather than the entire GAT, significantly reducing the overhead while maintaining accurate address mapping for the affected regions.
Solution Approach 2:
The system performs preliminary organization of the GAT into aligned and unaligned pages, allowing the cache to pre-load only the necessary unaligned page when needed. This preliminary structuring enables faster access and reduces overhead by avoiding unnecessary loading of aligned pages that don't require special handling.
Data Source
AI summary
An apparatus is provided that includes a non-volatile memory and a memory controller coupled to the non-volatile memory. The memory controller is configured to access a global address table (GAT) that maps logical addresses of a host to physical addresses of the non-volatile memory, receive a request from the host to write first data to the non-volatile memory, determine that the first data comprises fragmented data that are not aligned to a minimum write unit of the non-volatile memory, and create an unaligned GAT page, wherein the unaligned GAT page comprises a logical-to-physical mapping for the first data.