Gate Activity Analysis for Bespoke Microprocessor Area Reduction
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Solution Overview
Problem
Emerging applications such as wearables, implantables, and IoT devices face severe area and power constraints due to the inefficiency of general-purpose microprocessors, which contain unnecessary logic that consumes power and increases area usage.
Innovation Solution
An automated method using gate-level symbolic simulation to identify and eliminate unused logic from microprocessor IP cores, generating bespoke processors tailored to specific applications, resulting in reduced area and power consumption without performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general purpose microprocessors are used to support arbitrary applications, then adaptability is improved, but area consumption increases due to unnecessary logic gates
Solution Approach 1:
The patent extracts and removes unused logic gates from the microprocessor design through automated gate activity analysis. By simulating application execution and identifying gates that never toggle, the method extracts only the necessary logic components, eliminating unnecessary gates that consume area without contributing to functionality.
Solution Approach 2:
The patent applies local quality by making different parts of the processor have different properties based on their usage. Gates that are frequently used retain their full functionality, while unused gates are removed entirely. This creates a customized processor where each component's presence or absence is optimized for its specific role in the target application.
2Adaptability or versatility
If general purpose microprocessors are used to support arbitrary applications, then adaptability is improved, but power consumption increases due to unused gates
Solution Approach 1:
The patent extracts and removes unused logic gates that consume power without performing useful work. By identifying gates that never toggle during application execution and removing them, the method eliminates a significant source of static and dynamic power consumption while preserving all necessary functional capabilities.
3Use of energy by stationary object
If adaptive power management techniques are applied to reduce power consumption, then power efficiency is improved, but area inefficiency worsens due to domain isolation and state retention overhead
Solution Approach 1:
The patent performs preliminary action by identifying and removing unused gates before the processor is manufactured and deployed. Through automated gate activity analysis and simulation, the method determines which gates are unnecessary for the target application and eliminates them in advance, avoiding the need for runtime power management mechanisms that would add area overhead.
Data Source
AI summary
A method for analyzing a processor design includes receiving a design for a processor and receiving an application to be executed by the processor. The method includes simulating the execution of the application on the processor based on the design to identify unexercisable gates of the processor.