Gate Stack Air Gap Sealing for Uniform Capacitance Control
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Solution Overview
Problem
Current semiconductor manufacturing methods face challenges in forming uniform air gaps between gate electrodes, leading to non-uniform parasitic capacitance, gate stack bending, and reduced electrical performance due to uneven stress and incomplete sealing, which affects the reliability and write speed of semiconductor devices.
Innovation Solution
A method involving the formation of a sacrificial layer with controlled height and uniform profile, followed by a first insulating layer exposing end portions of gate stacks, and a second insulating layer sealing these spaces to create uniform air gaps with controlled dimensions, thereby reducing parasitic capacitance and improving structural reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If overhangs are formed on the tops of gate stacks to seal spaces between adjacent gate stacks, then air gaps can be formed between gate electrodes, but the overhangs exert uneven stress on the underlying gate stacks causing them to bend
Solution Approach 1:
A sacrificial layer is introduced as an intermediary material to temporarily occupy the spaces between gate stacks during the formation process. This sacrificial layer can be uniformly deposited and removed without creating overhang structures, thereby preventing uneven stress and gate stack bending while still enabling air gap formation. The sacrificial layer serves as a mediator that achieves sealing without the harmful mechanical effects of overhangs.
2Reliability
If conventional processes are used to form air gaps, then some air gaps can be created, but it is difficult to control the shapes and heights of the air gaps to be uniform, resulting in non-uniform parasitic capacitances
Solution Approach 1:
The invention controls the deposition parameters of the sacrificial layer to achieve uniform thickness and profile across the substrate. By precisely controlling deposition conditions such as temperature, pressure, and material flow rate, the sacrificial layer can be formed with high uniformity. This parameter control extends to the subsequent removal process, ensuring that air gaps of uniform shape and height are created, leading to consistent parasitic capacitance values across all gate electrode pairs.
3Reliability
If overhangs or capping layer partially fill the spaces between gate stacks, then the air gaps become smaller or the tops of air gaps are narrowed, but this is not conducive to interference decrease between gate electrodes
Solution Approach 1:
The invention extracts the harmful filling material (overhangs or capping layer material) from the air gap spaces by using a removable sacrificial layer approach. The sacrificial layer is deposited to define the air gap spaces, then selectively removed to create clean, unfilled air gaps between gate stacks. This extraction ensures that the air gaps maintain their full intended dimensions and volume, maximizing the reduction of parasitic capacitance while preserving structural integrity through the controlled deposition and removal process.
Data Source
AI summary
A semiconductor device includes several gate stacks over a substrate, a first insulating layer over the gate stacks and a second insulating layer. The gate stacks extend in the first direction and are separated from each other in the second direction. There is an air gap between two adjacent gate stacks. The first insulating layer is disposed over the gate stacks and the air gaps. The first insulating layer exposes an end portion of each of the gate stacks. The second insulating layer is disposed on the first insulating layer and further covers the end portions of the gate stacks that are uncovered by the first insulating layer.