Gate-Aligned Fin Cut Isolation for Dense FinFET Scaling

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Solution Overview

Problem

Conventional integrated circuit fabrication processes face challenges in maintaining mobility improvement and short channel control as device dimensions scale below the 10 nanometer node, particularly in multi-gate transistors like tri-gate transistors, due to constraints on lithographic processes and the trade-off between feature dimension and spacing.

Innovation Solution

Implementing a gate aligned fin cut isolation technique where fins are cut after gate patterning, allowing for self-aligned isolation with gate electrodes, reducing the need for multiple dummy gates and enhancing transistor density and strain maintenance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If conventional lithographic processes are used to pattern features, then the critical dimension can be reduced, but the spacing between features must be increased

Engineering Contradiction:
Improvecritical dimensionVSAvoidspacing between features
Core Design Contradiction:
Length of moving objectVSArea of stationary object

Solution Approach 1:

The fin structure is segmented into multiple fin segments by cutting the fin between gate structures. This segmentation allows each fin segment to be independently positioned and aligned with its corresponding gate, enabling reduced spacing between features while maintaining patternability. The fin is divided into discrete segments rather than remaining as a continuous structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from two-dimensional planar patterning to three-dimensional vertical alignment. By forming gates first and then cutting fins to align with the gates in the vertical dimension, the process achieves better spatial utilization. The fin segments are positioned at different vertical levels relative to the gates, allowing reduced lateral spacing while maintaining manufacturing precision.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If multiple dummy gates are used to maintain alignment, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvealignment precisionVSAvoidnumber of dummy gates
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The gate structures are formed in advance before the fin segments are positioned. By establishing the gate positions first as reference markers, subsequent fin cutting and alignment operations can be precisely performed relative to these pre-formed gates. This preliminary gate formation eliminates the need for dummy gates to maintain alignment.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The gate structures serve a dual function: they act as both the functional gate electrodes and as alignment reference markers for positioning the fin segments. This self-service approach eliminates the need for separate dummy gates that would otherwise be required solely for alignment purposes, reducing device complexity while maintaining manufacturing precision.

Inventive Principle:
Principle #25Self-service

3Device complexity

If fin isolation is not perfectly aligned with gate electrodes, then manufacturing complexity is reduced, but transistor density decreases

Engineering Contradiction:
Improvealignment complexityVSAvoidtransistor density
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

Gate structures are formed in advance to establish precise alignment references before fin isolation cutting. This preliminary gate formation enables the fin isolation to be perfectly aligned with the gate electrodes, maximizing transistor density without significantly increasing manufacturing complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The fin isolation is perfectly aligned specifically at the regions where gate electrodes are present, while other regions may have different isolation characteristics. This localized precision alignment at critical areas maximizes transistor density in the active regions without requiring perfect alignment everywhere, balancing manufacturing complexity with productivity.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20260052755A1Gate aligned FIN cut for advanced integrated circuit structure fabrication
Publication Date: 2026.02.19 INTEL CORP
  • US20260052755A1 patent drawing
  • US20260052755A1 patent drawing
  • US20260052755A1 patent drawing

AI summary

Gate aligned fin cut for advanced integrated circuit structure fabrication is described. For example, an integrated circuit structure includes a first fin segment having a fin end, and a second fin segment spaced apart from the first fin segment, the second fin segment having a fin end facing the fin end of the first fin segment. A first gate structure is over the first fin segment, the first gate structure substantially vertically aligned with the fin end of the first fin segment. A second gate structure is over the second fin segment, the second gate structure substantially vertically aligned with the fin end of the second fin segment. An isolation structure is laterally between the fin end of the first fin segment and the fin end of the second fin segment.