Gate-Aligned Contacts Using Self-Aligned Spacer-Defined Openings
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits poses challenges due to constraints on lithographic processes, particularly in achieving precise alignment and spacing of features, leading to a trade-off between critical dimension and feature spacing.
Innovation Solution
The method involves forming gate aligned contacts by creating a semiconductor structure with gate structures and contact plugs directly between sidewall spacers of adjacent gate structures, eliminating the need for a critical lithography step and using intrinsically selective wet etching to generate contact openings, thereby aligning contact patterns perfectly with existing gate patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional lithographic processes are used to pattern features in semiconductor stacks, then critical dimension can be reduced, but spacing between features becomes constrained
Solution Approach 1:
The patent applies preliminary action by forming contact openings using the gate pattern itself as a reference structure before final contact formation. The gate-aligned contact process uses the gate electrode and sidewall spacers as pre-formed structures to define contact locations, eliminating the need for separate lithographic patterning of contacts. This preliminary use of gate structures enables precise contact placement without being constrained by lithographic spacing limitations.
2Manufacturing precision
If tight lithographic registration is used to align contact patterns with gate patterns, then alignment precision is improved, but process complexity and difficulty increase
Solution Approach 1:
The patent implements self-service by making the gate pattern itself serve as the alignment reference for contact formation. The gate electrode and sidewall spacers automatically define the contact locations through their physical presence and geometric relationships. This self-aligning mechanism eliminates the need for separate lithographic alignment steps and complex registration processes, as the gate structures themselves provide the alignment framework.
Solution Approach 2:
The sidewall spacers act as an intermediary element that translates the gate pattern into contact openings. The spacers are formed on the sidewalls of the gate electrode and serve as a physical template that defines where contact openings should be located. This intermediary structure mediates between the gate pattern and the final contact positions, ensuring precise alignment without requiring direct lithographic registration between separate patterns.
3Ease of manufacture
If conventional contact formation processes are used, then manufacturing steps are standardized, but fabrication efficiency decreases
Solution Approach 1:
The patent merges multiple process steps into a unified gate-aligned contact formation sequence. Instead of separately patterning contacts, forming contact holes, and then aligning them to gates, the process combines these steps by using the gate structures themselves to define contact locations. The formation of sidewall spacers and subsequent contact openings occurs in an integrated sequence that eliminates redundant lithographic and alignment steps, improving fabrication efficiency while maintaining standardization through consistent use of gate structures as references.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of gate aligned contacts without the need for tight lithographic registration, improving the efficiency of semiconductor structure fabrication and reducing the complexity of the process, while maintaining precise alignment and spacing.
Implementation Method 1
using intrinsically selective wet etching to generate contact openings
Data Source
AI summary
Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.