Gate-Aligned Contacts Using Self-Aligned Wet-Etched Openings
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits poses challenges due to constraints on lithographic processes, particularly in achieving precise alignment and spacing of features, leading to a trade-off between critical dimension and feature spacing.
Innovation Solution
The method involves forming gate aligned contacts by creating a semiconductor structure with gate structures and contact plugs directly between sidewall spacers of adjacent gate structures, eliminating the need for tight lithographic registration and using intrinsically selective wet etching to generate contact openings, thereby simplifying the contact formation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to pattern features in semiconductor stacks, then feature spacing can be controlled, but the critical dimension becomes limited by lithographic constraints
Solution Approach 1:
The patent applies preliminary action by forming contact openings using the gate structure itself as a self-aligned mask before final contact formation. The gate structure is first patterned with precise critical dimensions, then contact openings are created directly between gate structures using the gates as alignment references, eliminating the need for separate lithographic steps that would otherwise limit critical dimension precision.
Solution Approach 2:
The patent uses an intermediary approach by introducing a sacrificial material layer between the gate structures that defines the contact opening positions. This sacrificial layer acts as a mediator that translates the gate structure geometry into precisely positioned contact openings, allowing the critical dimension to be defined by the gate structure rather than by subsequent lithographic processes.
2Manufacturing precision
If additional lithography steps are used to achieve precise contact alignment, then contact positioning accuracy improves, but process complexity increases
Solution Approach 1:
The patent applies self-service by making the gate structure serve its dual function as both the transistor control element and the alignment reference for contact formation. The gate structure automatically defines the positioning of contact openings through self-aligned processes, eliminating the need for separate lithography and alignment steps that would increase process complexity.
Solution Approach 2:
The patent merges multiple functions into the gate structure formation process. The same gate patterning process that creates the transistor gates also establishes the alignment framework for contact formation, combining what would traditionally be separate lithography steps into a unified process flow that reduces overall complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of gate aligned contacts without the need for additional lithography steps, improving the precision and efficiency of contact formation while reducing the complexity of the process, thereby addressing the scaling challenges in multi-gate transistor fabrication.
Implementation Method 1
using intrinsically selective wet etching to generate contact openings
Data Source
AI summary
Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.