Gate-All-Around Semiconductor Device With 3D Source and Drain
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices, the gate all around structure faces challenges in scaling and controlling current without increasing gate length, while also suppressing short channel effects, which existing technologies have not adequately addressed.
Innovation Solution
A semiconductor device with a wire pattern spaced apart from a substrate, surrounded by a gate electrode, and featuring source and drain regions connected to the wire pattern, with gate spacers and insulating layers to enhance performance and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate length is increased to control current, then current control improves, but the device area increases and scaling is hindered
Solution Approach 1:
The gate electrode is configured to surround the wire pattern in a three-dimensional manner, extending in multiple directions including circumferential direction and vertical direction. This 3D gate structure provides enhanced current control without increasing the planar device footprint, as the gate control is achieved through spatial arrangement rather than increasing gate length in a single direction.
Solution Approach 2:
The gate electrode is positioned to surround the wire pattern, with the gate spacer formed on the sidewalls of the gate electrode. This nested configuration allows the gate to control current from multiple directions simultaneously, achieving superior current control without requiring increased gate length.
2Productivity
If scaling is achieved using 3D channel, then device density increases, but manufacturing precision requirements increase
Solution Approach 1:
The wire pattern is formed first as a sacrificial structure, followed by formation of the gate electrode surrounding it, and then the gate spacer is formed on the gate sidewalls. This sequential formation process with the wire pattern as a template simplifies alignment requirements compared to forming all structures simultaneously, as each subsequent structure is positioned relative to the previously formed wire pattern.
Solution Approach 2:
The wire pattern serves as an intermediary sacrificial structure that defines the position and dimensions of the channel region. This intermediary approach simplifies the manufacturing process by providing a physical template for subsequent gate and spacer formation, reducing the complexity of direct alignment between multiple critical structures.
3Reliability
If the source and drain areas are widened to decrease resistance, then resistance decreases, but the device area increases
Solution Approach 1:
The source and drain regions are extended not only in the horizontal direction but also in the vertical direction, forming elevated structures. This 3D expansion of source and drain areas increases the effective contact area and decreases resistance without proportionally increasing the planar device footprint, as part of the area increase occurs in the vertical dimension.
Data Source
AI summary
A semiconductor device includes a wire pattern spaced apart from a substrate and extended in a first direction, a gate electrode disposed around a circumference of the wire pattern and extended in a second direction that is different from the first direction, a source disposed on a first side of the gate electrode, a drain disposed on a second side of the gate electrode, the source and the drain connected to the wire pattern and a gate spacer disposed on first and second sidewalls of the gate electrode, on the source and on the drain.