Gate-All-Around Backside Contacts for Leakage-Safe Source/Drain Layout
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices has led to the need for improved electrical characteristics and reliability, particularly in semiconductor devices with three-dimensional structures to overcome the limitations of planar metal oxide semiconductor FETs.
Innovation Solution
The semiconductor device incorporates insulating patterns with protrusions, a substrate insulating layer, device isolation layers, channel layers, gate structures that vertically overlap the insulating patterns, and source/drain regions with backside contact structures, where the insulating patterns partially penetrate through the gate structures, enhancing electrical connectivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If insulating patterns are made to protrude from the device isolation layer to reduce leakage current, then reliability is improved, but the vertical distance between channel layers and insulating patterns increases, potentially affecting electrical characteristics
Solution Approach 1:
The patent transitions from a planar insulating pattern configuration to a three-dimensional structure where insulating patterns protrude vertically from the device isolation layer. This dimensional change allows the insulating patterns to extend into the vertical space between the device isolation layer and the lowermost channel layer, effectively reducing leakage current paths while maintaining appropriate electrical distances.
Solution Approach 2:
The insulating patterns are selectively positioned to protrude only in specific regions where leakage current reduction is most critical. The protrusions are localized between the device isolation layer and the lowermost channel layer, providing targeted electrical isolation where needed without unnecessarily increasing vertical distances in other regions.
2Productivity
If backside contact structures are positioned close to gate electrodes to improve device integration, then productivity is improved, but the short margin between them reduces reliability
Solution Approach 1:
The patent utilizes the vertical dimension to position backside contact structures at different height levels relative to gate electrodes. By extending contact structures vertically and positioning them at appropriate heights, the design achieves close horizontal integration while maintaining sufficient vertical clearance to prevent electrical shorting between contact structures and gate electrodes.
Data Source
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AI summary
A semiconductor device includes: insulating patterns (102) spaced apart from each other in a first direction (Fig. 2 left-hand side) and in a second direction (Fig. 2 middle) that intersects the first direction; a substrate insulating layer (194) on first side surfaces of the insulating patterns; a device isolation layer (110) on second side surfaces of the insulating patterns; channel layers (142) on the insulating patterns and spaced apart from each other in a vertical direction that is perpendicular to an upper surface of the device isolation layer; gate structures (162, 165) vertically overlapping the insulating patterns, surrounding each of the channel layers, and extending in the second direction; source/drain regions (150A, 150B) provided outside the gate structures; and backside contact structures (216, 195) electrically connected to the source/drain regions and provided below the source/drain regions, wherein the insulating patterns include protrusions protruding in the vertical direction from an upper surface of the device isolation layer (110), and, in a region in which the insulating patterns vertically overlap the gate structures, a vertical distance (D2) between a lower surface of a lowermost channel layer among the channel layers and an upper surface of the protrusions is greater than a vertical distance (D1) between the channel layers.