Gate-All-Around Semiconductor Fabrication via Selective Capping Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor device fabrication methods face challenges in scaling and controlling current without increasing gate length, particularly in effectively suppressing the short channel effect in gate-all-around structures.
Innovation Solution
The method involves forming fin-type structures with alternating semiconductor patterns on a substrate, followed by capping layers of different materials, and then removing dummy gate electrodes to create wire pattern groups, allowing for the formation of gate electrodes surrounding the wire patterns, which enables improved current control and reduced short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-all-around structure is used for scaling, then current controlling capability is improved and short channel effect is suppressed, but manufacturing complexity increases due to multiple capping layers and selective removal processes
Solution Approach 1:
The patent divides the semiconductor structure into distinct regions with different capping layer configurations. First and second regions are segmented such that the first region has a first capping layer while the second region has a second capping layer, allowing selective processing and simplifying the overall manufacturing complexity while maintaining the gate-all-around structure benefits
Solution Approach 2:
The patent applies preliminary actions by forming dummy gate electrodes on both capping layers before selective removal. This preliminary structuring enables controlled subsequent processing where specific capping layers and underlying semiconductor patterns are removed in a predetermined sequence, managing complexity through planned multi-step processing
2Reliability
If gate-all-around structure is used to suppress short channel effect, then device performance is improved, but manufacturing precision requirements increase due to alternating semiconductor patterns and selective etching
Solution Approach 1:
The patent implements local quality by creating different capping layer structures in different regions. The first capping layer and second capping layer have different properties and are selectively processed, allowing tailored etching conditions for different areas and reducing overall precision requirements while maintaining local structural integrity for effective gate-all-around formation
Solution Approach 2:
The patent uses capping layers as intermediary protective structures during selective removal processes. These intermediary layers protect underlying semiconductor patterns during etching, enabling precise formation of gate-all-around structures without requiring direct high-precision etching of the semiconductor material itself
3Adaptability or versatility
If wire patterns with different materials are formed in different regions, then device functionality is enhanced, but process steps increase due to selective capping layer removal
Solution Approach 1:
The patent merges multiple functions into the capping layer structure. The first and second capping layers serve both as protective layers during processing and as region-defining structures that enable subsequent selective removal to create different wire patterns. This merging reduces the need for separate processing sequences and minimizes overall process complexity while achieving material diversity
Data Source
AI summary
A method of fabricating a semiconductor device includes forming first and second fin-type structures on first and second regions of a substrate, respectively, forming first and second capping layers on the first and second fin-type structures, respectively, forming a first dummy gate electrode on the first capping layer and a second dummy gate electrode on the second capping layer, exposing the first capping layer and the second capping layer by removing the first dummy gate electrode and the second dummy gate electrode, forming a second wire pattern group on the second region, and forming a first wire pattern group on the first region.