Gate Stack Quality for Gate-All-Around FETs
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Solution Overview
Problem
Conventional gate stack channels in GAA FETs face challenges in simultaneously achieving reliability anneal and multi-threshold voltage due to limited spacing, which restricts the ability to perform effective annealing processes without regrowth of interfacial layers.
Innovation Solution
The method involves forming dielectric material in separate deposition processes to achieve reliability annealing and multi-threshold voltage processing with a reduced thermal budget, using a modified high-k dielectric profile and laser anneal, allowing for improved gate stack quality and preventing interfacial layer regrowth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional gate stack channels are used with limited spacing, then device density is improved, but the ability to perform effective annealing processes without interfacial layer regrowth deteriorates
Solution Approach 1:
The gate stack channel is segmented into multiple nanosheets separated by dielectric material layers. This segmentation increases the effective spacing between channels, allowing annealing processes to be performed without causing interfacial layer regrowth, while still achieving high device density through vertical stacking
Solution Approach 2:
The patent transitions from planar 2D channels to vertical 3D nanosheet structures. By stacking multiple nanosheets vertically with dielectric material in between, the effective channel length is increased without increasing the lateral footprint, enabling both high density and effective annealing
2Reliability
If dielectric material thickness is increased to prevent interfacial layer regrowth, then reliability is improved, but threshold voltage control precision deteriorates
Solution Approach 1:
Different regions of the gate stack have different dielectric material thicknesses. The dielectric material thickness is locally optimized between nanosheets to prevent interfacial layer regrowth during annealing, while the overall gate stack structure maintains precise threshold voltage control through controlled electrical characteristics
Solution Approach 2:
The patent changes the dielectric material thickness parameter within specific ranges (e.g., 1-5 nm) to achieve the optimal balance between preventing interfacial layer regrowth and maintaining threshold voltage control. This parameter optimization allows simultaneous achievement of reliability and precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances gate stack quality, reduces negative-bias temperature instability, and achieves a threshold voltage shift based on the thickness of the dielectric material, improving the performance of GAA FETs.
Implementation Method 1
performing an anneal process after forming the first metal oxide layer to achieve a threshold voltage (Vt) shift based on a thickness of the first portion of the dielectric material
Implementation Method 2
using a modified high-k dielectric profile and laser anneal, allowing for improved gate stack quality and preventing interfacial layer regrowth
Data Source
AI summary
A semiconductor device includes a first gate-all-around field-effect transistor (GAA FET) device including a first gate stack having first channels, interfacial layers formed around the first channels, and dielectric material including first and second portions having respective thicknesses formed on the first interfacial layers. The semiconductor device further includes a second GAA FET device including a second gate stack having second channels, the interfacial layers formed around the second channels, and the dielectric material formed on the second interfacial layers. A threshold voltage (Vt) shift associated with the semiconductor device is achieved based on a thickness of the first portion of the dielectric material.