Gate-All-Around Semiconductor Structure for Leakage Control
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Solution Overview
Problem
In semiconductor manufacturing, the reduction in device size leads to high leakage current issues due to the continuous decrease in the thickness of conventional gate dielectric layers, which existing technologies struggle to address effectively.
Innovation Solution
A method is developed to form a semiconductor structure with a gate structure that surrounds channel laminates, where the depth and width of trenches formed on either side of the gate structure vary to optimize the placement of spacers and sacrificial layers, allowing for a metal gate structure that gradually increases channel regions controlled by the gate, thereby reducing turn-on resistance and improving current density uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the thickness of conventional gate dielectric layer is continuously decreased to reduce device size, then device scaling is achieved, but leakage current increases
Solution Approach 1:
The patent changes the dielectric constant parameter by replacing conventional silicon dioxide gate dielectric material with high k gate dielectric material. This allows maintaining a thin physical thickness for scaling while achieving higher effective capacitance, thereby reducing leakage current without sacrificing device miniaturization
Solution Approach 2:
The patent employs a composite gate structure combining high k gate dielectric material with metal gate electrode. This composite approach leverages the high dielectric constant of the first material to reduce leakage while the metal gate avoids Fermi level pinning and boron penetration effects, solving multiple issues simultaneously
2Reliability
If the gate structure surrounds channel laminates from all directions, then channel controlling capability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the gate structure into distinct components: high k gate dielectric layer and metal gate electrode layer, formed in separate sequential steps. The channel laminates are also segmented into multiple thin layers with sacrificial layers between them. This segmentation enables controlled formation of each component while achieving the overall gate-all-around structure
Solution Approach 2:
The patent performs preliminary actions by first forming the channel laminates with sacrificial layers, then forming the gate structure around them, and finally removing the sacrificial layers to create voids. This preliminary placement of sacrificial layers simplifies the subsequent gate formation process and enables the gate-all-around structure to be achieved more easily
3Ease of manufacture
If uniform trenches are formed on both sides of gate structure, then manufacturing process is simplified, but current density uniformity deteriorates
Solution Approach 1:
The patent applies local quality by forming trenches with different depths at different locations. The first trenches adjacent to the fin have a first depth, while the second trenches between channel laminates have a second depth greater than the first depth. This localized variation in trench depth allows precise control of spacer positions to achieve uniform current density across different channel regions
Solution Approach 2:
The patent introduces asymmetry in the trench configuration by making the depths of trenches at different locations unequal. The second trenches are deliberately made deeper than the first trenches, creating an asymmetric pattern that compensates for variations in channel characteristics and improves current density uniformity across the device
Data Source
AI summary
A semiconductor structure and a method for forming same are provided. The forming method includes: providing a substrate, a fin protruding from the substrate, and at least two channel laminates sequentially located on the fin, where each channel laminate includes a sacrificial layer and a channel layer; forming a gate structure across the channel laminates; forming, in the channel laminates, a groove that exposes the fin, where after the groove is formed, the fin, the channel layer adjacent to the fin, and the remaining sacrificial layer encircle a first trench, adjacent channel layers and the remaining sacrificial layer between the adjacent channel layers encircle a second trench; forming first spacers in the first trench and the second trench; and forming a source-drain doping layer in the groove.