Gate-All-Around Nanosheet FET Tapering for Electrostatic Control
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Solution Overview
Problem
Nanosheet technology faces scaling and performance challenges beyond 45 nm due to the tendency of wide channels to perform as double gate configurations rather than true Gate-All-Around configurations, which are less ideal for electrostatic control.
Innovation Solution
A semiconductor device with bi-directional taper profiles in both the Y- and X-directions, featuring nanosheets with varying widths and lengths, and a substrate with a tapered surface, allowing for co-optimization of Contacted-gate-Pitch (CPP) scaling, subthreshold slope, contact resistance, and drive current requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If nanosheet channel width is increased to maximize drive current, then drive current is improved, but electrostatic control deteriorates because the channel performs as double gate rather than true Gate-All-Around configuration
Solution Approach 1:
The patent applies local quality by creating non-uniform nanosheet structures with varying widths along the channel length. Different regions of the nanosheet have different widths (W1, W2, W3) to optimize local electrostatic control while maintaining overall drive current. This allows each section to have tailored properties for its specific function.
Solution Approach 2:
The patent employs asymmetry by introducing tapered profiles in the nanosheet channels. The channels have asymmetric width variations along their length, creating true Gate-All-Around configuration in certain regions while maintaining enhanced drive current in other regions. This asymmetric design breaks the symmetry that causes double-gate behavior in uniform wide channels.
2Ease of manufacture
If uniform nanosheet width is used to simplify manufacturing, then manufacturing complexity is reduced, but device performance is limited due to inability to optimize different channel regions
Solution Approach 1:
The patent applies segmentation by dividing the nanosheet channel into multiple sections with different width characteristics. The channel is segmented into regions with different widths (W1, W2, W3) along its length, allowing each segment to be optimized for specific performance requirements while maintaining a relatively simple continuous structure.
Solution Approach 2:
The patent utilizes parameter changes by varying the nanosheet width parameter along the channel length. The width transitions from W1 to W2 to W3 in different regions, creating a tapered profile that optimizes both electrostatic control and drive current without requiring complex manufacturing processes.
3Device complexity
If all nanosheets have identical dimensions to simplify device design, then design complexity is reduced, but performance optimization is limited due to inability to co-optimize CPP scaling and subthreshold slope
Solution Approach 1:
The patent applies dynamics by introducing variability in nanosheet dimensions rather than using static uniform dimensions. The nanosheets have dynamic width variations along their length, allowing the device to achieve multiple performance optimizations simultaneously through the tapered profiles and different width sections.
Data Source
AI summary
A semiconductor device comprising a first nanosheet located on top of a substrate, wherein the first nanosheet is tapered the Y-direction to have a width W1 and the first nanosheet is tapered in the X-direction to have a length L1. A second nanosheet located on top of the first nanosheet, wherein the second nanosheets is tapered in the Y-direction to have a width W2 and the first nanosheet is tapered in the X-direction to have a length L2. Wherein the widths W1 and W2 are different from each other and the lengths L1 and L2 are different from each other and wherein the substrate includes a tapered surface in the Y-direction.