Gate-All-Around Nanowire Structures With Selective Backside Depopulation
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Solution Overview
Problem
The challenge of scaling multi-gate and nanowire transistors is exacerbated by the constraints on lithographic processes, leading to a trade-off between feature dimension and spacing, which complicates the fabrication of transistors with varying drive currents and leakage currents, particularly in nanowire and nanoribbon architectures.
Innovation Solution
A selective backside removal approach is employed to depopulate nanowire or nanoribbon channels, allowing for modulation of drive currents by varying the number of wires or ribbons through patterning and etching, while maintaining top ribbons in place, and enabling flexible device performance metrics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional front-side fin depopulation methods are used to fabricate transistors with varying drive currents, then device performance can be modulated, but capacitance penalties increase and manufacturing complexity increases
Solution Approach 1:
The patent inverts the conventional approach by performing fin depopulation from the backside of the substrate rather than the front side. This allows selective removal of fins to modulate drive currents while avoiding the capacitance penalties associated with front-side methods, as the backside approach enables cleaner separation of depopulated regions from active device regions
Solution Approach 2:
The substrate is divided into front and back sides, with the backside used specifically for fin depopulation operations. This segmentation allows independent optimization of device formation (front side) and fin removal (back side), reducing unwanted capacitive coupling and simplifying the overall manufacturing process
2Length of moving object
If lithographic processes are used to pattern nanowire and nanoribbon channels, then feature dimensions can be controlled, but spacing constraints increase and manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from two-dimensional planar patterning to three-dimensional vertical structures by forming nanowire and nanoribbon channels that extend through the substrate thickness. This dimensional change allows control of channel dimensions through vertical epitaxial growth rather than lateral lithography, thereby reducing spacing constraints and manufacturing precision requirements
Solution Approach 2:
The patent changes the controlling parameter for feature dimension from lateral lithographic patterning to vertical epitaxial growth parameters. By controlling channel length, width, and composition through deposition processes rather than photolithography, the method achieves precise dimensional control while avoiding the spacing and precision limitations of conventional lithographic approaches
3Productivity
If multi-gate and nanowire transistors are scaled to smaller dimensions, then device density increases, but short channel control and mobility improvement become more difficult to maintain
Solution Approach 1:
The patent employs composite material structures including nanowire channels formed from alternating layers of different semiconductor materials (e.g., Si/SiGe). These composite structures provide both the density benefits of scaling and the electrical properties needed for short channel control, as the material composition can be engineered to optimize carrier mobility and threshold voltage characteristics
Solution Approach 2:
The patent implements gate structures that completely surround the nanowire channels in a nested configuration, with the gate electrode wrapping around the channel from all sides. This gate-all-around geometry provides superior electrostatic control over the channel compared to planar gates, enabling maintenance of short channel control even as device dimensions are reduced to increase density
Data Source
AI summary
Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a backside removal approach, are described. For example, an integrated circuit structure includes a first insulator sub-fin structure over a first stack of nanowires. A second insulator sub-fin structure is over a second stack of nanowires, the second stack of nanowires having a greater number of nanowires than the first stack of nanowires, and the second insulator sub-fin structure having a vertical thickness less than a vertical thickness of the first insulator sub-fin structure. A first gate electrode is around the first stack of nanowires, and a second gate electrode is around the second stack of nanowires.