Gate-All-Around Semiconductor Device Parasitic Capacitance Reduction
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Solution Overview
Problem
The reduction in size of semiconductor devices leads to increased parasitic capacitance and electrical resistance, exacerbating short channel effects and current leakage, particularly due to the decrease in gate width and channel length, which affects the gate channel characteristics and generates excessive electric fields.
Innovation Solution
A semiconductor device design where the gate electrode is positioned in an insulation layer under an active fin with a gate structure that includes a thicker portion filling the channel trench, reducing parasitic capacitance by limiting the overlap area between the contact structure and the gate structure, and expanding the surface area of the contact and gate structures to stabilize electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate electrode width is decreased to reduce device size, then the device integration density is improved, but the parasitic capacitance between the gate electrode and adjacent contact increases
Solution Approach 1:
The gate electrode is positioned in an insulation layer beneath the active fin structure, transitioning from a planar side-by-side arrangement to a vertical stacked arrangement. This dimensional change separates the gate electrode from adjacent contacts in the lateral direction, reducing parasitic capacitance while maintaining high integration density through vertical space utilization
Solution Approach 2:
An insulation layer is introduced as an intermediary between the gate electrode and adjacent contact structures. This intermediate insulating layer acts as a barrier that reduces the parasitic capacitance coupling between the gate electrode and nearby contacts, allowing for closer spacing and higher integration density
2Productivity
If the gate electrode width is decreased to reduce device size, then the device integration density is improved, but the electrical resistance of the gate electrode increases
Solution Approach 1:
The gate electrode extends in the vertical direction beneath the active fin, creating a three-dimensional structure with increased surface area. This vertical extension compensates for the reduced lateral width by providing additional conduction pathways, thereby maintaining electrical conductivity while achieving higher integration density
Solution Approach 2:
The gate electrode geometry is changed from a thin lateral structure to a vertically extended structure with increased height and surface area. This parameter change in the vertical dimension compensates for the reduced lateral dimensions, maintaining electrical resistance performance while enabling smaller device footprint
3Productivity
If the channel length is decreased to reduce device size, then the device integration density is improved, but the short channel effect deteriorates gate channel characteristics
Solution Approach 1:
The gate electrode wraps around the channel structure in a gate-all-around configuration, providing control from multiple directions including top, bottom, and sidewalls. This three-dimensional gate control compensates for the reduced channel length by enhancing electric field confinement and improving threshold voltage control, thereby mitigating short channel effects
Solution Approach 2:
The gate structure is segmented into multiple portions with different thicknesses: a first portion with greater thickness for enhanced control over the channel, and a second portion with lesser thickness. This segmentation allows optimized control of gate channel characteristics while maintaining compact device dimensions for high integration density
4Productivity
If the gate electrode width is decreased, then the device size is reduced, but the overlap area between gate electrode and contact increases causing excessive electric field
Solution Approach 1:
The gate electrode is repositioned in the vertical dimension beneath the active fin structure, separating it from adjacent contacts in the lateral dimension. This vertical stacking reduces the lateral overlap area between gate and contact, thereby reducing the intensity of electric fields and preventing gate-induced drain leakage while maintaining compact device size
Data Source
AI summary
Semiconductor devices are provided. A semiconductor device includes a channel. The semiconductor device includes a gate structure having first and second portions. The channel is between the first and second portions of the gate structure. A contact structure is adjacent a portion of a side surface of the channel. Related methods of forming semiconductor devices are also provided.