Gate-All-Around Semiconductor Fabrication via Hydrogen Plasma
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Solution Overview
Problem
Current semiconductor device fabrication methods face challenges in achieving efficient scaling and improving channel mobility due to surface roughness and Ge-rich phenomena, which affect threshold voltage and mobility.
Innovation Solution
A method involving the formation of alternating semiconductor layers on a substrate, partial removal of layers to expose patterns, and subsequent heat-treatment using hydrogen plasma to reduce Ge concentration and improve surface roughness, forming a gate-all-around structure with improved channel characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication methods are used to form semiconductor structures, then manufacturing process is simpler, but surface roughness increases and Ge-rich phenomena occur, degrading channel mobility and threshold voltage stability
Solution Approach 1:
The method performs preliminary actions by forming a complete stack of alternating semiconductor layers with different etch selectivities before any removal operations. This preliminary structured formation enables subsequent selective removal processes to achieve smooth surfaces and control Ge concentration, resolving the contradiction between manufacturing precision and process complexity by preparing the system in advance for controlled modification.
Solution Approach 2:
The invention changes material parameters by using semiconductor layers with different etch selectivities (e.g., SiGe vs Si, or III-V materials vs Si) to enable selective removal. This parameter change allows the etching process to differentiate between layers, achieving smooth surfaces and controlling Ge distribution without requiring complex additional processing steps, thus improving manufacturing precision while managing process complexity.
2Reliability
If Ge concentration is increased to improve channel characteristics, then mobility improves, but surface roughness and Ge-rich phenomena worsen, degrading device reliability
Solution Approach 1:
The method applies local quality by creating alternating layers with different Ge concentrations and etch selectivities. The selective removal process then locally modifies the structure to achieve smooth surfaces in critical areas while maintaining appropriate Ge concentration in channel regions. This local differentiation resolves the contradiction by allowing high Ge concentration where needed for mobility while preventing Ge-rich phenomena and surface roughness where they would degrade reliability.
3Productivity
If multi-gate transistor scaling is implemented to increase device density, then productivity improves, but manufacturing precision challenges increase due to surface roughness and Ge-rich phenomena
Solution Approach 1:
The invention transitions from two-dimensional planar structures to three-dimensional multi-gate structures by forming alternating semiconductor layers that extend vertically. The selective removal process then creates wire patterns and gate-all-around structures that fully surround the channel in three dimensions. This dimensional change enables continued scaling and increased device density while the controlled etching process maintains manufacturing precision by preventing surface roughness and Ge-rich phenomena through the use of layers with different etch selectivities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and driving current characteristics of semiconductor devices by reducing Ge concentration and surface roughness, thereby improving channel mobility and threshold voltage stability.
Implementation Method 1
treating the first semiconductor patterns remaining on the exposed first wire pattern group
Implementation Method 2
vaporizing the first semiconductor patterns remaining on the exposed first wire pattern group
Data Source
AI summary
A method of fabricating a semiconductor device is provided. The method includes forming a first fin structure which includes first semiconductor patterns and second semiconductor patterns stacked alternately on a substrate and extends in a first direction, forming an exposed first wire pattern group which includes the second semiconductor patterns by removing the first semiconductor patterns, heat-treating the exposed first wire pattern group, and forming a first gate electrode which surrounds the first wire pattern group and extends in a second direction different from the first direction.