Gate-All-Around Semiconductor Device Manufacturing with Organic and Cross-Linking Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor device miniaturization is to effectively integrate high-capacity and high-performance devices by reducing the size and spacing of semiconductor elements, which existing technologies have not adequately addressed, particularly in achieving efficient manufacturing methods for gate-all-around transistor structures with different work function metal layers.
Innovation Solution
A method for manufacturing gate-all-around semiconductor devices involves forming semiconductor patterns on a substrate, creating a gate dielectric layer, and using different work function metal layers with specific organic and cross-linking layers to achieve the desired structure, including forming sacrificial patterns and conductive patterns to define the channel regions and gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate-all-around transistor structures with multiple work function metal layers are manufactured using conventional methods, then device integration density can be increased, but manufacturing complexity and defect rates increase due to multiple patterning and etching processes
Solution Approach 1:
The patent divides the gate structure into multiple work function metal layers (first work function metal layer and second work function metal layer) that are formed separately and stacked. This segmentation allows each layer to be optimized independently for different threshold voltage requirements, enabling high-density integration while maintaining manageable manufacturing complexity through modular construction
Solution Approach 2:
The patent forms the first work function metal layer and its associated organic pattern and cross-linking layer before forming the second work function metal layer. This preliminary action sequence establishes a stable foundation and protects underlying structures, reducing defects during subsequent manufacturing steps while enabling complex multi-layer integration
2Quantity of substance
If conventional manufacturing processes are used for multi-layer work function metal structures, then device capacity can be increased, but etching precision deteriorates due to over-etching affecting adjacent patterns
Solution Approach 1:
The patent introduces organic patterns and cross-linking layers as intermediary protective structures between the work function metal layers and the etching process. These intermediary layers act as etch masks that prevent over-etching from affecting adjacent patterns, thereby maintaining high etching precision while enabling the formation of high-capacity multi-layer devices
Solution Approach 2:
The patent forms organic patterns and cross-linking layers beforehand to cushion and protect the underlying substrate and previously formed structures during the etching of subsequent layers. This prior cushioning prevents harmful over-etching effects, ensuring manufacturing precision is maintained throughout the multi-layer fabrication process
3Reliability
If work function metal layers with different properties are formed to achieve different threshold voltages, then device performance is improved, but process control difficulty increases
Solution Approach 1:
The patent utilizes parameter changes by selecting different work function metal materials with distinct electrical properties for the first and second work function metal layers. This allows precise control of threshold voltages for different transistor types (n-type and p-type), improving device performance while maintaining process control through well-established material selection and deposition parameter optimization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the efficient integration of high-performance semiconductor devices with multiple threshold voltages by reducing defects and preventing over-etching during the manufacturing process, thereby enhancing the integration density and performance of semiconductor elements.
Implementation Method 1
the converting the portion of the organic layer into the cross-linking layer includes diffusing an acid of the first organic pattern into the organic layer
Data Source
AI summary
A semiconductor device manufacturing method includes forming a gate dielectric layer surrounding first semiconductor patterns and second semiconductor patterns; forming a first organic pattern covering the second semiconductor patterns; forming a sacrificial pattern interposed between the first semiconductor patterns and exposing both side surfaces of the first semiconductor patterns, and a conductive pattern surrounding the second semiconductor patterns and disposed between the first organic pattern and the second semiconductor patterns; forming a second organic pattern covering the first semiconductor patterns, the gate dielectric layer, the sacrificial pattern, and the first organic pattern; and forming a cross-linking layer interposed between the first organic material pattern and the second organic material pattern.