Gate-All-Around Semiconductor Device With Stacked Channels
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Solution Overview
Problem
The increasing demand for high-performance semiconductor devices with fine patterns and multifunctionality poses challenges in manufacturing, particularly in overcoming limitations of planar MOSFETs and FinFETs, such as physical scaling and performance limitations, which existing technologies have not adequately addressed.
Innovation Solution
A semiconductor device design featuring an active pattern with vertically spaced channel layers, gate electrodes that surround the channels, source/drain regions, and a semiconductor structure with alternately stacked layers, along with a blocking layer to enhance reliability and protect against damage during manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar MOSFET or FinFET structures are used, then manufacturing is simpler, but physical scaling and performance limitations occur
Solution Approach 1:
The patent transitions from planar (2D) MOSFET channels to vertically stacked 3D channel structures, enabling continued scaling by adding a vertical dimension. Multiple channel layers are stacked vertically to increase device capacity without further reducing lateral dimensions, overcoming the physical scaling limitations of planar devices.
Solution Approach 2:
The patent implements gate electrodes that completely surround each channel layer in a gate-all-around (GAA) configuration, with multiple such structures nested vertically. Each channel layer is enclosed by its own gate electrode, creating a nested arrangement that provides superior electrostatic control compared to partial-gate configurations.
2Reliability
If gate-all-around structures are implemented, then electrostatic control is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the channel structure into multiple discrete channel layers, each surrounded by its own gate electrode. This segmentation allows independent formation and control of each gate-channel interface, simplifying the manufacturing process compared to attempting to form a single complex gate structure around a monolithic 3D channel.
Solution Approach 2:
The patent forms the channel layers and gate electrodes in a sequential bottom-up manner, with each layer and gate prepared in advance before assembly. The alternating stacking of channel and gate materials allows preliminary preparation of individual layers, reducing the complexity of forming the complete GAA structure in a single complex process.
3Reliability
If fine patterns are integrated, then device performance is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent moves critical dimensions from the lateral plane to the vertical stacking direction, where finer control can be achieved through atomic-layer deposition techniques. The vertical stacking of channel and gate layers enables precise thickness control without requiring equally precise lateral patterning, reducing the burden on lithography precision.
4Productivity
If vertically stacked channel layers are used, then device density is increased, but reliability during manufacturing processes decreases
Solution Approach 1:
The patent employs alternating stacking of different semiconductor materials (e.g., Si/SiGe) for channel and sacrificial layers. These composite structures provide mechanical strength and structural support during manufacturing processes, preventing damage to the delicate vertical stack while enabling high device density. The different materials offer complementary properties that enhance overall structural reliability.
Data Source
AI summary
A semiconductor device includes an active pattern extending on a substrate in a first direction, divided into a plurality of regions by a separation region, and having a first edge portion exposed toward the separation region; first, second and third channel layers vertically separated and sequentially disposed on the active pattern; a first gate electrode extending in a second direction, intersecting the active pattern, and surrounding the first, second and third channel layers; source/drain regions disposed on the active pattern, on at least one side of the first gate electrode, and contacting the first, second and third channel layers; a semiconductor structure including first semiconductor layers and second semiconductor layers alternately stacked on the active pattern, and having a second edge portion exposed toward the separation region; and a blocking layer covering at least one of an upper surface, side surfaces, or the second edge portion, of the semiconductor structure.