Gate-All-Around Semiconductor Device with Stacked Channels
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high integration, speed, and reliability due to complex internal structures, which hinder their ability to meet increasing demands for high-speed, multifunctional, and cost-effective electronics.
Innovation Solution
The semiconductor device design incorporates an insulating layer on a substrate with vertically spaced channel patterns, a gate pattern surrounding the channel patterns, and source/drain patterns positioned relative to the gate pattern, allowing for efficient integration and manufacturing of gate-all-around structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistor structures are used, then manufacturing processes are simple, but device performance and integration density are limited
Solution Approach 1:
The patent transitions from conventional planar (2D) transistor structures to three-dimensional vertically stacked channel patterns. Multiple channel patterns are stacked vertically above each other, with gate electrodes wrapping around the channels from all sides (gate-all-around structure). This vertical stacking in the third dimension dramatically increases the effective channel width and integration density within the same footprint area, directly resolving the contradiction between integration density and structural complexity.
Solution Approach 2:
The gate electrodes are designed to surround and wrap around the vertically stacked channel patterns from all sides, creating a nested configuration where the gate encompasses the channel. This gate-all-around structure provides superior electrostatic control over the channel while maximizing the use of vertical space. The nested arrangement allows multiple functional layers (channels, gates, source/drain regions) to be integrated in a compact vertical stack, thereby increasing integration density without proportionally increasing lateral footprint.
2Speed
If vertically stacked channel patterns with gate-all-around structures are implemented, then device performance and speed are improved, but manufacturing complexity increases
Solution Approach 1:
The vertically stacked structure is divided into discrete, repeating units comprising channel patterns, gate electrodes, and source/drain regions. Each stack consists of multiple identical or similar channel-gate units arranged vertically. This segmentation into modular units allows for standardized manufacturing processes where the same fabrication steps can be repeatedly applied to create uniform stacks, thereby managing manufacturing complexity while achieving high device performance through the stacked configuration.
3Adaptability or versatility
If higher integration and more complex internal structures are adopted, then device functionality increases, but manufacturing cost increases
Solution Approach 1:
The vertically stacked channel-gate structure serves multiple functions simultaneously: it provides high integration density, delivers superior electrostatic control through gate-all-around configuration, enables high-speed operation, and maintains compatibility with existing semiconductor fabrication processes. The modular stacked design can be adapted for different device types (logic transistors, memory devices) and scaling requirements, making it a universal solution that achieves enhanced functionality without proportionally increasing manufacturing complexity or cost.
Data Source
AI summary
A semiconductor device includes an insulating layer on a substrate, a first channel pattern on the insulating layer and contacting the insulating layer, second channel patterns on the first channel pattern and being horizontally spaced apart from each other, a gate pattern on the insulating layer and surrounding the second channel patterns, and a source/drain pattern between the second channel patterns.