Gate-All-Around Stacked-Channel Transistors for Short-Channel Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling down of Integrated Circuits (ICs) has increased complexity in processing and manufacturing, necessitating advancements in Fin Field-Effect Transistor (FinFET) structures and methods, particularly in improving the short channel effect and carrier mobility.
Innovation Solution
The development of FinFETs with Gate-All-Around (GAA) structures involves forming semiconductor fins with multiple channels and performing anti-punch-through implantation before channel material formation, followed by oxidation and epitaxial growth of source/drain regions to enhance channel integrity and reduce impurity scattering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FinFET scaling down is performed to increase functional density, then the number of interconnected devices per chip area increases, but the short channel effect worsens and manufacturing complexity increases
Solution Approach 1:
The patent implements Gate-All-Around (GAA) structures that wrap the gate electrode completely around the channel in three dimensions, transitioning from planar 2D gate control to 3D surround control. This dimensional change provides superior electrostatic control over the channel, effectively suppressing the short channel effect while enabling continued scaling for higher functional density
2Productivity
If FinFET geometry is scaled down to increase device density, then more devices fit per chip area, but impurity scattering increases and carrier mobility decreases
Solution Approach 1:
The patent employs selective doping strategies where different regions of the transistor structure receive different doping treatments. The channel region maintains low doping to minimize impurity scattering and preserve carrier mobility, while source/drain regions and other areas receive appropriate doping for electrical contact and device operation. This local quality differentiation allows high device density without sacrificing carrier mobility in the critical channel region
3Ease of manufacture
If conventional FinFET structures are used, then manufacturing process is simpler, but drive current is insufficient for advanced technology nodes
Solution Approach 1:
The patent transitions from planar FinFET structures to three-dimensional Gate-All-Around configurations, where the gate wraps completely around the channel. This 3D structure increases the effective gate control area and improves carrier injection efficiency, significantly boosting drive current while maintaining compatibility with existing semiconductor manufacturing processes through adapted fabrication sequences
4Reliability
If multiple processing steps are added to improve channel integrity, then short channel effect is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent performs anti-punch-through implantation before channel material formation, establishing protective doping profiles in advance. This preliminary action prevents punch-through effects during subsequent processing steps without requiring additional complex interventions later in the manufacturing sequence, thereby maintaining channel integrity while controlling overall process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the drive current and reduces the short channel effect by providing multiple channels and eliminating impurity scattering, resulting in enhanced performance of FinFETs.
Implementation Method 1
The semiconductor strips are oxidized to form dielectric rings encircling remaining portions of the semiconductor strips
Data Source
AI summary
A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.