Gate-All-Around Transistor Core Region Isolation
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Solution Overview
Problem
Existing transistor manufacturing technologies, particularly at nodes below 5 nm, face challenges in achieving optimal on-current and off-current characteristics due to the thickness of the gate dielectric layer affecting the performance of input/output devices in FinFETs, where the gate dielectric layer thickness impacts the channel length and device performance.
Innovation Solution
A method involving the formation of a gate-all-around structure using a silicon-germanium and silicon epitaxial layer, followed by photolithography and etching to create fins, and then forming a metal gate that surrounds the gate dielectric and work function layers, allowing for improved channel formation without compromising the gate dielectric layer thickness in input/output devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate-all-around structure is formed using silicon-germanium and silicon epitaxial layers, then the short channel effect in core devices is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent segments the device into core device regions and input/output device regions, with different gate structures for each. The gate-all-around structure is specifically applied to core devices where short channel effect improvement is critical, while input/output devices use conventional structures. This segmentation allows targeted improvement without applying complex processes universally.
Solution Approach 2:
The patent applies different gate structure qualities to different regions: gate-all-around structures with silicon-germanium/silicon epitaxial layers are used locally in core device regions where short channel effect control is most needed, while input/output regions use simpler structures. This local quality approach optimizes performance where required without unnecessarily complicating the entire device.
2Reliability
If the gate dielectric layer thickness is increased to improve input/output device performance, then the on-current and off-current characteristics improve, but the channel length effectively decreases affecting core device performance
Solution Approach 1:
The patent segments the device into core device regions and input/output device regions, with different gate structures for each. The gate-all-around structure is specifically applied to core devices where short channel effect improvement is critical, while input/output devices use conventional structures. This segmentation allows targeted improvement without applying complex processes universally.
Solution Approach 2:
The patent applies different gate structure qualities to different regions: gate-all-around structures with silicon-germanium/silicon epitaxial layers are used locally in core device regions where short channel effect control is most needed, while input/output regions use simpler structures. This local quality approach optimizes performance where required without unnecessarily complicating the entire device.
3Stability of the object's composition
If the wire size is reduced to increase gate dielectric layer thickness, then the gate dielectric layer can be thicker, but the device density increases and manufacturing precision requirements increase
Solution Approach 1:
The patent uses composite materials consisting of silicon-germanium epitaxial layers and silicon epitaxial layers stacked together to form the gate structure. This composite approach allows precise control of the effective gate dielectric thickness through material composition and layer stacking, rather than relying solely on reducing wire size, thereby maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the short channel effect in core devices while maintaining optimal on-current and off-current performance for input/output devices by isolating active regions and forming a gate-all-around structure that does not depend on the thickness of the gate dielectric layer, thus improving device performance without sacrificing wire size.
Implementation Method 1
forming an epitaxial layer on the surface of the semiconductor substrate, wherein the epitaxial layer includes at least one stacking layer formed by a silicon-germanium epitaxial layer and a silicon epitaxial layer
Data Source
AI summary
A method for manufacturing a transistor device includes a field oxide layer isolates an active region of a core device region from an active region of an input/output device region on a semiconductor substrate, the active region of the core device region is exposed by means of a mask layer, a gate-all-around structure is formed in the active region of the core device region, and a fin gate structure is formed in the active region of the input/output device region, thereby the on-current and off-current performance of the input/output device is not affected when the short channel effect of the core device is improved.