Gate-All-Around Transistor Layers for Higher Current and Lower Threshold
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Solution Overview
Problem
The challenge of forming reliable semiconductor devices at smaller sizes is exacerbated by the increasing complexity and difficulty of fabrication processes as feature sizes continue to decrease, necessitating improved manufacturing techniques to enhance device performance.
Innovation Solution
The integration of gate-all-around (GAA) transistor structures, which utilize semiconductor layers with different conductivity types to form bipolar junction transistors (BJTs) alongside MOSFETs, enhancing current flow and reducing threshold voltages through self-aligned patterning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process difficulty and device reliability worsen
Solution Approach 1:
The device is segmented into multiple functional regions including a first region with a first conductivity type and a second region with a second conductivity type. This segmentation allows each region to be optimized independently for its specific function, enabling the device to achieve high functional density while maintaining reliability through specialized design in each segment.
Solution Approach 2:
Different regions of the device are assigned different conductivity types and structural characteristics tailored to their specific functional requirements. The first region is optimized for one function while the second region is optimized for another, allowing local optimization that maintains overall device reliability even as feature sizes decrease.
2Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process complexity worsens
Solution Approach 1:
The fabrication process is segmented into distinct stages for forming different conductivity type regions. By dividing the device into separate first and second regions that can be formed through different process sequences, the overall fabrication complexity is managed while maintaining high functional density in the final product.
Solution Approach 2:
The first region with the first conductivity type is formed before the second region with the second conductivity type. This preliminary action allows subsequent processing steps to be simplified, as the foundation structure is already in place, thereby reducing overall fabrication process complexity despite decreasing feature sizes.
3Ease of manufacture
If conventional transistor structures are used at smaller sizes, then manufacturing simplicity is maintained, but device performance and current flow capability worsen
Solution Approach 1:
The transistor structure is segmented into multiple regions with different conductivity types, where each segment contributes to overall device performance. This segmented approach maintains manufacturing simplicity by using standard fabrication techniques while achieving enhanced performance through the synergistic combination of different conductivity regions.
Solution Approach 2:
The device employs a composite structure combining regions of different conductivity types (n-type and p-type) within a single transistor architecture. This composite approach enables the device to achieve superior performance characteristics including enhanced current flow capability while remaining compatible with conventional manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively increases drain current and reduces threshold voltage, thereby improving the performance of semiconductor devices by boosting current and efficiency in on-state operations.
Implementation Method 1
forming a semiconductor layer with a different conductivity type on the sidewall of the transistor channel to create a bipolar junction transistor (BJT) structure
Data Source
AI summary
A method includes forming a first semiconductor layer over a substrate; forming a dummy material covering a first sidewall of the first semiconductor layer; forming source/drain epitaxy structures over the substrate and in contact with the first semiconductor layer; forming an interfacial layer on a top surface and a second sidewall of the first semiconductor layer that are uncovered by the dummy material; removing the dummy material to expose the first sidewall of the first semiconductor layer; forming a second semiconductor layer on the first sidewall of the first semiconductor layer after removing the dummy material, in which the second semiconductor layer and the source/drain epitaxy structures have different conductivity types; and forming a gate electrode over the interfacial layer.