Gate-All-Around Transistors for Integration Density and Electrical Performance
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving increased reliability, performance, and integration density to meet demands for high-speed and low-power electronic devices, particularly in vertical-type field effect transistors where complexity and integration are necessary.
Innovation Solution
The semiconductor device design includes a substrate with active patterns and gate electrodes arranged in specific distances, featuring impurity regions and channel regions stacked perpendicular to the substrate, allowing for improved carrier mobility and electric characteristics through a gate-all-around transistor configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between adjacent active patterns is reduced to increase integration density, then the number of transistors per unit area increases, but short-channel effects and electrical performance deteriorate
Solution Approach 1:
The patent transitions from planar gate configuration to a three-dimensional gate-all-around structure that completely surrounds the channel region. This vertical dimension allows for better electrostatic control of the channel without reducing the horizontal pitch between active patterns, thus maintaining electrical performance while increasing integration density through vertical stacking of impurity regions and channel layers
Solution Approach 2:
The gate electrode is nested within a recess that completely surrounds the channel region, with the gate wrapped around the channel in a nested configuration. This nested structure provides maximum gate control over the channel while allowing compact arrangement of multiple active patterns, enabling higher integration density without compromising the electrostatic control needed for reliable operation
2Productivity
If vertical-type field effect transistors are implemented to increase integration density, then the number of devices per unit area increases, but manufacturing complexity increases
Solution Approach 1:
The semiconductor layer is segmented into multiple impurity regions (first, second, third impurity regions) and channel regions stacked vertically, with each segment serving a specific function. This segmentation allows for selective doping and independent optimization of source/drain and channel regions, simplifying the manufacturing process by enabling separate formation steps for each functional region rather than requiring complex monolithic structures
Solution Approach 2:
The gate electrode is formed in a recess that is preliminarily prepared around the channel region before final device completion. This preliminary formation of the gate-all-around structure establishes the fundamental device architecture early in the manufacturing process, providing a template for subsequent steps and reducing overall manufacturing complexity by setting the three-dimensional configuration before additional layers are added
Data Source
AI summary
A semiconductor device includes a substrate with an upper surface and a lower surface, and first to third active patterns extending from the upper surface of the substrate. The first to third active patterns are arranged adjacent to each other in a first direction. The second active pattern is disposed between the first and third active patterns. The semiconductor device also includes a first gate electrode surrounding side surfaces of the first and second active patterns, and a second gate electrode surrounding side surfaces of the third active pattern. Each of the first to third active patterns includes a first impurity region, a channel region, and a second impurity region.