Gate Conductive Layer Amorphization for CMOS Stress Memory
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Solution Overview
Problem
The use of SiGe as the main component in the source/drain region of transistors, combined with the stress-transfer-scheme (STS) technology, is hindered by the over-high thermal budget of the SiGe epitaxy process, which reduces the stress memory effect on the gate conductive layer, thereby limiting the enhancement of ion performance in CMOS devices.
Innovation Solution
A pre-amorphous implantation (PAI) process is performed before the rapid thermal annealing (RTA) process to amorphize the gate conductive layer, followed by the formation and subsequent removal of the STS, ensuring that the stress memory effect is maintained and utilized to enhance ion performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SiGe epitaxy process is performed at high temperature (700-900°C) for 3-4 hours to form source/drain region, then the source/drain region can be effectively formed with good material properties, but the gate conductive layer is recrystallized into polysilicon, losing the amorphous structure needed for stress memory effect
Solution Approach 1:
The patent applies preliminary amorphous implantation to the gate conductive layer before the SiGe epitaxy process. This pre-treatment ensures that even after the high-temperature epitaxy, the gate conductive layer maintains its amorphous structure and can effectively store stress from the STS, thereby resolving the contradiction between forming quality source/drain regions and preserving gate layer structure.
2Ease of manufacture
If ion implantation is performed at low energy in source/drain extension region before SiGe epitaxy, then the process sequence is maintained, but the gate conductive layer is not completely amorphized, resulting in insufficient stress memory effect
Solution Approach 1:
The patent changes the energy parameter of the ion implantation process from low energy to high energy (50-150 keV). This parameter change ensures complete amorphization of the gate conductive layer while maintaining the established process sequence, thereby achieving both ease of manufacture and effective stress memory effect.
3Reliability
If STS is deposited after high energy ion implantation to amorphize gate conductive layer, then excellent stress memory effect is achieved, but the subsequent high-temperature SiGe epitaxy recrystallizes the gate layer, negating the stress memory benefit
Solution Approach 1:
The patent performs amorphous implantation as a preliminary action before STS deposition and SiGe epitaxy. This timing ensures the gate conductive layer is amorphized before any subsequent processes that might affect its structure, allowing it to maintain amorphous state and effectively store stress throughout the remaining fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The PAI process prevents the negative impact of the high thermal budget, allowing the stress memory effect to effectively enhance ion performance in CMOS devices by amorphizing the gate conductive layer and maintaining stress memory post-STS removal.
Implementation Method 1
a pre-amorphous implantation (PAI) process is performed before the rapid thermal annealing (RTA) process to amorphize the gate conductive layer
Implementation Method 2
The PAI process prevents the negative impact of the high thermal budget, allowing the stress memory effect to effectively enhance ion performance in CMOS devices by amorphizing the gate conductive layer
Implementation Method 3
followed by the formation and subsequent removal of the STS, ensuring that the stress memory effect is maintained and utilized to enhance ion performance
Data Source
AI summary
A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed.