Gate Structure Formation via Amorphous-to-Polycrystalline Annealing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor manufacturing lies in forming reliable devices at increasingly smaller sizes, as feature sizes decrease, making fabrication processes more difficult and complex.
Innovation Solution
The process involves forming a semiconductor device structure by patterning fins on a substrate, using a combination of photolithography and self-aligned processes, depositing amorphous and polycrystalline semiconductor layers, and performing annealing to improve grain diameter and etching yield, ultimately forming gate structures over the fins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency is improved and costs are lowered, but fabrication processes become more difficult and reliability decreases
Solution Approach 1:
The method performs preliminary annealing treatment on the amorphous semiconductor layer before patterning to crystallize it into a polycrystalline structure. This preliminary crystallization improves the material's etching properties and reduces void formation, thereby enhancing fabrication reliability at smaller feature sizes while maintaining high functional density
Solution Approach 2:
The invention changes the physical and chemical parameters of the semiconductor layer through controlled annealing processes. By adjusting temperature, time, and atmosphere parameters during annealing, the amorphous layer is transformed into a polycrystalline structure with improved etching yield and reduced voids, enabling reliable fabrication at reduced feature sizes
2Area of stationary object
If feature sizes are decreased to increase functional density, then chip area is reduced, but fabrication process complexity increases
Solution Approach 1:
The amorphous semiconductor layer is preliminarily annealed and crystallized before the patterning step. This preliminary crystallization creates a more uniform and etch-resistant structure, simplifying subsequent patterning processes and reducing the number of process steps needed to achieve reliable features at smaller sizes
Solution Approach 2:
The self-aligned spacer formation process uses the gate structure itself as a template to define the source and drain regions. This copying approach ensures precise alignment without requiring additional lithography steps, reducing fabrication complexity while enabling smaller feature sizes
3Ease of manufacture
If amorphous semiconductor layers are used for gate structures, then deposition is easier, but etching yield is poor and voids form
Solution Approach 1:
The invention changes the physical state of the semiconductor layer from amorphous to polycrystalline through controlled annealing. This parameter change dramatically improves etching yield while maintaining the deposition advantages of amorphous layers, and eliminates void formation by creating a more stable crystalline structure
Solution Approach 2:
The method utilizes the phase transition from amorphous to polycrystalline state through annealing treatment. This phase transition transforms the semiconductor layer's structural properties, improving etch resistance and eliminating voids while maintaining the ease of amorphous layer deposition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the etching yield and reduces voids in the semiconductor layers, improving the reliability and performance of semiconductor devices by minimizing critical dimension variations and repairing broken bonds, thus facilitating more efficient semiconductor device fabrication at smaller scales.
Implementation Method 1
annealing a first amorphous layer over a fin into a first polycrystalline layer
Implementation Method 2
annealing the first amorphous layer into a first polycrystalline layer
Data Source
AI summary
A method for forming a semiconductor device structure is provided. The method includes forming a first amorphous layer over a substrate. The substrate has a base portion and a first fin portion over the base portion, and the first amorphous layer covers the first fin portion. The method includes annealing the first amorphous layer to crystallize the first amorphous layer into a first polycrystalline layer. The method includes forming a second amorphous layer over the first polycrystalline layer. The method includes removing a first portion of the second amorphous layer and a second portion of the first polycrystalline layer under the first portion. The remaining second amorphous layer and the remaining first polycrystalline layer together form a first gate structure over and across the first fin portion.