Semiconductor Gate Structure Annealing Stress Management
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Solution Overview
Problem
The challenge in semiconductor manufacturing is reducing gate leakage current and improving electrical performance and yield, particularly due to stress issues caused by thermal expansion during annealing treatments in the fabrication of semiconductor structures with high-K gate dielectric layers, which can lead to cracking and degradation of the isolation effect between contact-hole plugs and gate structures.
Innovation Solution
A method involving the formation of a semiconductor structure with a base substrate, an interlayer dielectric layer, and a stacked structure, where at least a first portion of the stacked structure is removed from the top of the interlayer dielectric layer before annealing, reducing thermal expansion and contraction stress, and subsequently filling the opening with a metal layer to improve gate structure quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-K gate dielectric layer is formed on the interlayer dielectric layer and annealing treatment is performed, then the electrical performance of the semiconductor device is improved, but thermal expansion and contraction stress causes cracking and degradation of the isolation effect
Solution Approach 1:
The gate dielectric layer is segmented into two distinct parts: a first gate dielectric layer formed on the interlayer dielectric layer, and a second gate dielectric layer formed on the first gate dielectric layer. This segmentation allows differential thermal expansion management, where the first layer accommodates stress from annealing treatment while the second layer provides the high-K dielectric properties needed for electrical performance. The isolation structure is also segmented to extend into the opening, creating distinct functional zones that maintain isolation despite thermal stress.
Solution Approach 2:
Different regions of the gate dielectric structure are assigned different qualities and functions. The first gate dielectric layer is optimized for stress resistance and adhesion to the interlayer dielectric, while the second gate dielectric layer is optimized for high-K properties and electrical performance. The isolation structure is locally extended into the opening to provide enhanced isolation where needed, while maintaining overall device performance.
2Strength
If the stacked structure is removed from the top of the interlayer dielectric layer before annealing, then thermal expansion stress is reduced and cracking is minimized, but additional fabrication steps are required
Solution Approach 1:
The first gate dielectric layer is formed on the interlayer dielectric layer before the annealing treatment is performed. This preliminary action ensures that the gate dielectric layer is already in place to accommodate and manage the thermal expansion stress during subsequent annealing, preventing cracking and degradation. The isolation structure is also preliminarily extended into the opening to ensure isolation is established before final gate structure formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces gate leakage current and enhances the isolation effect between contact-hole plugs and gate structures, thereby improving the electrical performance and yield of the semiconductor device by minimizing stress-induced cracking and optimizing the formation of the gate structure.
Implementation Method 1
performing an annealing treatment on the base substrate
Implementation Method 2
stress issues may be easily generated in the stacked structure under the high temperature environment during the annealing treatment
Data Source
AI summary
A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a base substrate, and forming an interlayer dielectric layer on the base substrate and having an opening exposing surface portions of the base substrate. The method also includes forming a stacked structure on a bottom and sidewall of the opening and on a top of the interlayer dielectric layer. In addition, the method includes removing at least a first portion of the stacked structure from the top of the interlayer dielectric layer. Further, the method includes performing an annealing treatment on the base substrate, and forming a gate structure by filling the opening with a metal layer.