Gate-Around Transistors for Electrostatic Control
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Solution Overview
Problem
The scaling down of transistor gate lengths leads to short-channel effects, such as Drain-Induced Barrier Lowering and degradation of sub-threshold slope, compromising current control and transistor performance.
Innovation Solution
The development of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) with wrapped-around gates, also known as gate-around transistors, where the gate electrode wraps around all sides of the channel, including the top surface, sidewalls, and underneath the semiconductor strip, enhancing electrostatic control and reducing short-channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If gate length is scaled down to increase drive current, then transistor speed increases, but short-channel effects worsen and current control degrades
Solution Approach 1:
The gate electrode is extended from a planar configuration into the trench to wrap around the semiconductor strip, transitioning from two-dimensional to three-dimensional control. This allows the gate to control current flow from multiple spatial dimensions (top, sidewalls, and bottom), significantly improving electrostatic control and reducing short-channel effects while maintaining scaled dimensions
2Power
If gate length is scaled down, then drive current increases, but electrostatic control of channel deteriorates
Solution Approach 1:
The gate electrode is nested within the trench structure, wrapping around the semiconductor strip in a nested configuration. The gate dielectric is positioned between the gate electrode and the semiconductor strip, creating a nested arrangement that maximizes the gate's control over the channel while minimizing parasitic capacitance
Data Source
AI summary
A device includes a substrate, a semiconductor strip over the substrate, a gate dielectric wrapping around the semiconductor strip, and a gate electrode wrapping around the gate dielectric. A dielectric region is overlapped by the semiconductor strip. The semiconductor strip and the dielectric region are spaced apart from each other by a bottom portion of the gate dielectric and a bottom portion of the gate electrode.