Gate Structure Barrier for Isotropic Etching Control
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Solution Overview
Problem
In semiconductor devices, particularly in CMOS technologies using the replacement metal gate (RMG) process, undercutting during etching of metal layers in narrow trenches can lead to incorrect work function deposition, resulting in inappropriate threshold voltage settings for nMOS and pMOS transistors, especially as device dimensions shrink.
Innovation Solution
A method involving the formation of a barrier material in trenches between nMOS and pMOS regions to separate etching sections, allowing for selective etching of gate conductors and preventing undercutting, thereby enabling precise deposition of work function metals with different work functions for each region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If work function metal is deposited to adjust threshold voltage, then desired electrical characteristics are achieved, but incorrect deposition occurs due to undercutting
Solution Approach 1:
The patent segments the trench structure using sacrificial gates, creating isolated zones where work function metal deposition can occur independently in each region. This segmentation ensures that metal deposition for threshold voltage adjustment in one region does not affect adjacent regions, enabling precise and independent control of electrical characteristics for different device types (nMOS vs pMOS).
Solution Approach 2:
The patent performs preliminary action by depositing work function metal before removing the sacrificial gates. This sequence ensures that the work function metal is deposited on the complete trench surface including areas that will later be exposed after sacrificial gate removal. This preliminary deposition prevents subsequent deposition errors and ensures uniform threshold voltage control across the entire device structure.
2Productivity
If device dimensions are reduced to increase integration density, then productivity is improved, but undercutting becomes more severe
Solution Approach 1:
The patent applies segmentation by introducing sacrificial gates at regular intervals along the trench, dividing it into multiple smaller zones. This approach is particularly effective for scaled-down device dimensions where the trench width becomes comparable to the metal layer thickness. The segmentation prevents undercutting from spanning the entire trench width, making the process robust even as device dimensions are reduced to increase integration density.
Solution Approach 2:
The patent changes the structural parameters of the trench by introducing intermediate sacrificial gates, effectively transforming a single wide trench into multiple narrower zones. This parameter change allows the use of isotropic etching processes even in scaled technologies, maintaining etching control despite reduced device dimensions. The sacrificial gate spacing and dimensions are optimized based on the specific technology node to achieve the desired balance between integration density and etching control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures accurate work function deposition, achieving desired threshold voltages for both n-channel and p-channel transistors by preventing unwanted etching and allowing for isotropic etching in narrow trenches, thus improving the precision and reliability of semiconductor device fabrication.
Implementation Method 1
etching the first gate conductor material in the first trench section, wherein the mask and the barrier counteracts etching of the first gate conductor material in the second trench section
Implementation Method 2
forming a barrier in the hole by depositing a barrier material in the hole
Data Source
AI summary
The disclosed technology generally relates to semiconductor devices and more particularly to a gate structure for a semiconductor device, and to methods of forming the same. In an aspect a method for forming a gate structure includes forming a first set of one or more semiconductor features and a second set of one or more semiconductor features. The method additionally includes forming a sacrificial gate extending across the semiconductor features of the first set and the semiconductor features of the second set. The method additionally includes forming a hole by etching the sacrificial gate, wherein the sacrificial gate is divided into a first sacrificial gate section and a second sacrificial gate section, forming a barrier in the hole by depositing a barrier material in the hole, removing the first sacrificial gate section and the second sacrificial gate section by etching wherein a first trench section is formed and a second trench section is formed, forming a first gate conductor in the first trench section and the second trench section, forming a mask above the second trench section, the mask exposing the first trench section, etching the first gate conductor in the first trench section, wherein the mask and the barrier counteracts etching of the first gate conductor in the second trench section, and forming a second gate conductor in the first trench section.