Semiconductor Gate Structure GIDL Reduction via Barrier Layer Etching
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Solution Overview
Problem
Buried-channel array transistors in semiconductor devices experience increased gate-induced drain leakage (GIDL) due to a larger overlap area between the gate electrode and impurity regions, which reduces transistor reliability.
Innovation Solution
A method involving the formation of a precursor structure with patterned substrates, oxide, and nitride layers, followed by the deposition and selective removal of barrier layers using etchants like CF4 and NF3 to create a wrapped gate structure, reducing GIDL by optimizing the thickness and placement of barrier layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a buried-channel array transistor structure is used to increase integration density, then the effective channel length increases and device downsizing is achieved, but the gate induced drain leakage (GIDL) increases due to larger overlap area between gate electrode and impurity regions
Solution Approach 1:
The gate structure is divided into multiple segments with barrier layers (first barrier layer 150 and second barrier layer 170) positioned at different locations along the gate electrode 162. This segmentation creates multiple isolation zones that collectively reduce GIDL while maintaining the buried-channel configuration for high integration density.
Solution Approach 2:
Barrier layers (150, 170) are introduced as intermediary materials between the gate electrode 162 and the impurity regions. These barrier layers act as mediators that block the leakage current path while allowing the gate to maintain its control function over the channel, thus reducing GIDL without sacrificing integration density.
2Reliability
If barrier layers are added to reduce GIDL, then transistor reliability improves, but device complexity increases due to additional manufacturing steps
Solution Approach 1:
The formation of barrier layers is merged with existing gate structure fabrication steps. The first barrier layer 150 is formed before the gate electrode 162, and the second barrier layer 170 is formed after, integrating these reliability-enhancing features into the standard gate fabrication flow without requiring completely separate manufacturing processes.
Solution Approach 2:
The first barrier layer 150 is formed in advance before the gate electrode 162 is deposited. This preliminary action prepares the structure to reduce GIDL from the outset, and the second barrier layer 170 is subsequently added to further enhance the effect, building reliability into the structure progressively through the manufacturing sequence.
3Reliability
If selective removal of barrier layers is performed to optimize gate structure, then GIDL is reduced through precise thickness control, but manufacturing precision requirements increase
Solution Approach 1:
Different portions of the barrier layers are selectively removed to create local variations in thickness and composition. The first barrier layer 150 is partially removed, and the second barrier layer 170 is also partially removed, creating regions with different barrier properties that optimize GIDL reduction while managing manufacturing precision requirements through localized rather than uniform modification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively decreases GIDL, enhancing the reliability of the semiconductor device by improving the electric properties and integration density through precise control of the gate structure.
Implementation Method 1
A portion of the first barrier layer is removed with an etchant including CF4, C2F6, C3F8, C4F8, F2, NF3, SF6, CHF3, HF, COF2, ClF3 or H2O2 to expose a sidewall of the oxide layer
Implementation Method 2
the first gate structure is treated with a protectant including H2, NH3, CxHy and a combination thereof before removing the portion of the first barrier layer
Data Source
AI summary
A method of manufacturing a semiconductor device is provided. A precursor structure is formed, in which the precursor structure includes a patterned substrate having at least one trench therein, an oxide layer covering the patterned substrate, and a nitride layer on the oxide layer and exposing a portion of the oxide layer in the trench. A first barrier layer and a first gate structure is formed on the oxide layer. A portion of the first barrier layer is removed with an etchant including CF4, C2F6, C3F8, C4F8, F2, NF3, SF6, CHF3, HF, COF2, ClF3 or H2O2 to expose a sidewall of the oxide layer. A second barrier layer is formed on the first gate structure and the oxide layer. A portion of the second barrier layer is removed with the etchant. A second gate structure is formed on the second barrier layer.