Power Semiconductor Gate Bias Control for Gate Oxide Aging
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Solution Overview
Problem
Power semiconductor modules, particularly SiC MOSFETs, face significant reliability issues due to gate oxide degradation, which leads to increased failure probability, threshold voltage shifts, and subsequent performance degradation.
Innovation Solution
A method is proposed to monitor and adjust the gate voltage and switching times of power semiconductor modules based on the state of health of the gate oxide. This involves acquiring initial and current state of health values, deducing appropriate gate voltages and delay times, and generating control signals to apply these adjustments during operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a negative bias is applied to avoid self-turn-on during idle time, then reliability is improved, but threshold voltage shifts and device performance degrades
Solution Approach 1:
The patent applies dynamic adjustment of gate voltage bias based on real-time monitoring of threshold voltage drift. Instead of using a fixed negative bias, the system continuously adapts the compensation voltage to maintain stable threshold voltage while preventing self-turn-on during idle periods. This dynamic approach resolves the contradiction by making the bias condition responsive to actual device state rather than static.
Solution Approach 2:
The patent implements a feedback mechanism that monitors threshold voltage variations and adjusts the gate bias accordingly. The system measures the actual threshold voltage drift caused by negative bias application and uses this information to compensate and maintain stable device operation. This closed-loop feedback resolves the contradiction by using the very parameter that degrades (threshold voltage) to control the solution (bias adjustment).
2Reliability
If gate oxide field is limited in blocking mode and on-state, then substrate defect density is reduced, but device performance and switching capability is compromised
Solution Approach 1:
The patent applies periodic stress relief cycles where the gate oxide field is intentionally limited during specific time periods (idle times) to allow defect recovery, while maintaining full performance capability during active switching periods. This periodic alternation between protective mode and performance mode resolves the contradiction by distributing the stress over time rather than continuously compromising performance.
Solution Approach 2:
The patent applies preliminary protective measures by limiting gate oxide field stress during idle periods before the device is next activated. This preliminary action prevents defect accumulation that would otherwise occur during continuous operation, thereby reducing substrate defect density without affecting the device's full performance capability when actually needed.
3Reliability
If voltage spikes are avoided, then gate oxide quality is maintained, but switching speed and response time are reduced
Solution Approach 1:
The patent allows rapid voltage transitions (rushing through) during active switching periods when the device is intentionally operated, while applying protective voltage clamping during idle periods. This skipping approach resolves the contradiction by concentrating the high-speed operation in brief intervals when gate oxide stress is acceptable, while using protective measures during extended idle periods to maintain gate oxide quality.
Data Source
AI summary
A treatment method of a power semiconductor module comprising at least one semiconductor element including a Metal-Oxide-Semiconductor element and/or a Metal-Insulator-Semiconductor element, said method comprising:a. acquiring a first value Vsoh,0 corresponding, to an initial state of health of a gate oxide of the module;b. acquiring a second value Vsoh,X corresponding, to a current state of health of a gate oxide of the module;c. deducingan ON-state gate voltage VCC or an OFF-state gate voltage VEE, anda delay time of the turn-on tON or a delay time of the turn-off tOFF in function of said acquired first value Vsoh,0 and said second value Vsoh,X;d. generating at least one control signal configured to apply the deduced gate voltage VCC or VEE to the module during the deduced delay time tON or tOFF.