Gate Boosting Transmission Gate With Very-Low-Threshold P-Channel Transistors

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Solution Overview

Problem

The existing integrated circuit technology faces challenges in overdriving p-channel transistors in transmission gates due to the difficulty in providing a negative bias, which complicates the design and limits the scalability of field-programmable gate arrays (FPGAs) as it requires additional circuitry and negative power supply.

Innovation Solution

Fabricating p-channel transistors as very-low-threshold devices allows for easier overdriving by biasing the gate above VDD in the off state, providing additional drive without increasing leakage, thus enabling overdrive on both n-channel and p-channel transistors without additional circuitry.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If p-channel transistors are overdriven by providing negative bias voltage, then transmission gate speed is improved, but device complexity and power supply requirements worsen

Engineering Contradiction:
Improvetransmission gate speedVSAvoidpower supply complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent changes the threshold voltage parameter of the p-channel transistor by using a very-low-threshold device instead of a standard-threshold device. This allows the transistor to be effectively overdriven with a positive voltage (VDD+0.2V) rather than requiring negative bias voltage, thus improving transmission gate speed without complicating the power supply architecture

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

Instead of applying negative voltage to overdrive the p-channel transistor gate (the conventional approach), the patent inverts the approach by using a very-low-threshold device that can be effectively overdriven with positive voltage. This inversion eliminates the need for negative power supply while achieving the same overdrive effect

Inventive Principle:
Principle #13The other way round (Inversion)

2Loss of energy

If standard-threshold p-channel transistors are used, then leakage is reduced, but overdrive capability worsens

Engineering Contradiction:
Improveleakage currentVSAvoidoverdrive capability
Core Design Contradiction:
Loss of energyVSEase of operation

Solution Approach 1:

The patent changes the threshold voltage parameter from standard to very-low-threshold for the p-channel transistor. This parameter change enables effective overdrive with positive voltage while the transistor design maintains acceptable leakage characteristics through proper sizing and threshold selection

Inventive Principle:
Principle #35Parameter changes

3Speed

If n-channel transistors are overdriven with positive voltage, then transmission gate speed is improved, but area consumption worsens

Engineering Contradiction:
Improvetransmission gate speedVSAvoidtransmission gate area
Core Design Contradiction:
SpeedVSArea of stationary object

Solution Approach 1:

The patent changes the threshold voltage parameter of the p-channel transistor to very-low-threshold, which enables effective overdrive with positive voltage. This symmetric overdrive approach for both n-channel and p-channel transistors optimizes the area-speed tradeoff by allowing smaller transistor sizes to achieve the same speed performance

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9484904B2Gate boosting transmission gate
Publication Date: 2016.11.01 MICROSEMI SOC CORP
  • US9484904B2 patent drawing
  • US9484904B2 patent drawing

AI summary

A gate-boosting transmission gate includes an input node and an output node. An n-channel transistor has a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the n-channel transistor having a low threshold. A p-channel transistor has a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the p-channel transistor having a very low threshold.