Semiconductor Gate Bridge Channel for Low-Resistance Interconnects
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Solution Overview
Problem
Existing methods for forming electrical connections between metal gates in PMOS and NMOS devices during high-K/metal gate replacement in SRAMs result in unstable and high-resistance connections due to material isolation and non-selective back-etching, which complicates uniform thickness control and device height maintenance.
Innovation Solution
A semiconductor element structure with a bridge channel embedded in a recess connecting the gates, formed by partially removing the gates to create a recess and filling it with a conductive material, ensuring a stable and sufficient electrical connection without altering the device height or requiring back-etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If CMP dishing space is used for electrical connection, then connection space is provided, but the space is too thin to maintain sufficient electrical connection and results in overly high electrical resistance
Solution Approach 1:
The patent transitions from using a thin horizontal dishing space (2D surface approach) to creating a vertical recess structure (3D volume approach). The recess extends downward from the gate surface, providing sufficient volume for conductive material while maintaining appropriate thickness for reliable electrical connection between gates.
2Quantity of substance
If back-etching is performed to create connection space, then connection space is obtained, but uniform thickness control becomes difficult and device height is compromised
Solution Approach 1:
The recess structure is formed in advance during the gate replacement process, before final gate assembly. This preliminary formation allows precise control of the connection space geometry and ensures uniform thickness characteristics are maintained throughout the manufacturing process.
3Quantity of substance
If back-etching is performed to create connection space, then connection space is obtained, but the height of the semiconductor device is compromised
Solution Approach 1:
The conductive material for electrical connection is nested within the recess structure that is itself integrated into the gate region. This nesting approach allows the connection space to be formed within the existing gate volume rather than requiring additional height, thus preserving the overall device height.
4Reliability
If high-K materials are directly converted to metals, then electrical connection is realized, but the method is not stable and reliable
Solution Approach 1:
The patent introduces a recess structure as an intermediary form between the high-K material and the final metal gate assembly. This intermediate structure provides a controlled pathway for conductive material deposition, ensuring stable and reliable electrical connection while maintaining processability.
Data Source
AI summary
A method for forming a semiconductor element structure is provided. First, a substrate including a first MOS and a second MOS is provided. The gate electrode of the first MOS is connected to the gate electrode of the second MOS, wherein the first MOS includes a first high-K material and a first metal for use in a first gate, and a second MOS includes a second high-K material and a second metal for use in a second gate. Then the first gate and the second gate are partially removed to form a connecting recess. Afterwards, the connecting recess is filled with a conductive material to form a bridge channel for electrically connecting the first metal and the second metal.