Gate Busbar Layout for Uniform Signal Timing in Power Semiconductor Cells
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Solution Overview
Problem
The increasing demand for high power and high frequency applications in power semiconductor devices leads to larger chip sizes with more cells connected in parallel, resulting in significant parasitic parameters in the gate busbar that cause signal delay and uneven current distribution, particularly under high frequency conditions.
Innovation Solution
A semiconductor device with a gate busbar featuring non-uniform lengths and widths or thicknesses of emitter segments and gate busbar portions to ensure consistent gate signal arrival at each cell, achieved by varying the dimensions of the gate busbar portions along specific axes to compensate for distance from the gate pad.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the chip size is increased to meet high power demand, then the power handling capability is improved, but the parasitic parameters of the gate busbar increase causing signal delay
Solution Approach 1:
The gate busbar is divided into multiple segments with different widths along its length. The width varies locally to compensate for the increased distance from the gate pad to cells at different positions. Specifically, the gate busbar has a larger width near the gate pad and gradually decreases toward the periphery, creating local variations in electrical characteristics that balance the signal propagation time across the large chip area.
2Power
If more cells are connected in parallel to increase power output, then the power capability is improved, but the current distribution becomes uneven among cells
Solution Approach 1:
The gate busbar width is locally adjusted at different positions to compensate for the varying distances from the gate pad to individual cells. Cells closer to the gate pad are served by wider gate busbar sections, while cells farther away are served by narrower sections. This local variation in gate busbar dimensions balances the RC time constants, ensuring that all cells receive gate signals at approximately the same time and share current uniformly.
Solution Approach 2:
The physical dimensions (width) of the gate busbar are changed as a parameter to control the electrical characteristics. By varying the width along the length of the gate busbar, the resistance and capacitance are adjusted to compensate for distance effects, thereby equalizing the gate signal arrival time and current distribution across all parallel-connected cells.
3Reliability
If the gate busbar width is increased to reduce resistance, then the signal transmission is improved, but the parasitic capacitance increases causing more severe signal delay at high frequency
Solution Approach 1:
The gate busbar width is changed as a controllable parameter that varies along its length. Instead of using a uniform width, the width is optimized at different positions to balance the RC time constant. This parameter variation allows the design to achieve low resistance where needed while controlling capacitance to minimize signal delay, particularly at high frequencies where parasitic effects are most pronounced.
Data Source
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Figure 3a~4
Figure 5a~5b
AI summary
The present invention provides a semiconductor device having a plurality of cells, each of the plurality of cells includes a gate. The semiconductor device includes a gate pad, a gate busbar and a plurality of gate lines. The gate busbar connects the gate pad to the plurality of gate lines, the plurality of gate lines connects the gate busbar to the gates of the plurality of cells, and each of the plurality of gate lines is disposed along a first axis. The gate busbar includes a plurality of first portions each disposed along a second axis, the second axis intersects with the first axis. The plurality of first portions are spaced apart from each other to divide the semiconductor device into a plurality of emitter segments. Lengths of the plurality of emitter segments along the first axis changes with distances of the plurality of emitter segments from the gate pad, such that gate signals arriving at the gates of the plurality of cells from the gate pad via the gate busbar and the plurality of gate lines are substantially consistent.