Gate Cap Layer Structure for Self-Aligned Contact Isolation
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Solution Overview
Problem
As semiconductor device dimensions decrease, the thickness of sidewall spacers in self-aligned contacts (SACs) becomes thinner, leading to potential short circuits between source/drain contacts and gate electrodes, necessitating improved electrical isolation.
Innovation Solution
The implementation of a method that forms two cap layers over the gate electrode, which serve as contact-etch stop layers, and uses different materials for these cap layers and the second etch-stop layer to achieve etching selectivity during contact hole formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the thickness of sidewall spacer is reduced to increase device density, then device density increases, but electrical isolation between source/drain contacts and gate electrodes deteriorates
Solution Approach 1:
The patent divides the contact-etch stop function into multiple separate layers (first cap layer and second cap layer) with different materials and etching resistances. This segmentation allows each layer to provide isolation protection at different stages of the etching process, ensuring reliable electrical isolation even when sidewall spacer thickness is reduced for higher device density.
Solution Approach 2:
The patent forms cap layers over the gate electrode structure before forming the source/drain contacts. These pre-formed cap layers serve as protective barriers during subsequent etching operations, preventing premature contact hole formation and ensuring that electrical isolation is maintained throughout the manufacturing process.
2Reliability
If multiple cap layers are formed to improve electrical isolation, then electrical isolation improves, but manufacturing complexity increases
Solution Approach 1:
The patent designs the cap layers to serve multiple functions simultaneously: the first cap layer provides etch protection during initial contact hole formation, while the second cap layer provides protection during subsequent processing steps. This multi-functionality allows the structure to maintain reliable electrical isolation without proportionally increasing manufacturing complexity, as the same layers serve multiple protective roles.
Solution Approach 2:
The patent utilizes differences in etching resistance parameters between the first and second cap layers to achieve selective etching. By selecting materials with distinct etching characteristics, the process enables selective removal of specific layers while preserving others, simplifying the manufacturing process compared to using multiple identical layers that would require separate processing for each.
3Manufacturing precision
If different materials are used for cap layers and etch-stop layer to achieve etching selectivity, then etching selectivity improves, but material selection and process control complexity increases
Solution Approach 1:
The patent assigns different material properties to different layers based on their specific functional requirements. The first cap layer uses a material optimized for protection during initial etching, while the second cap layer and etch-stop layer use materials optimized for their respective protection and stopping functions. This local optimization of material properties achieves high etching selectivity while keeping process control manageable through clear functional differentiation.
Data Source
AI summary
In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first sidewall spacers is different from a second depth of the first space above the first gate electrode layer.