Gate Cap Layer Dishing Prevention via Sacrificial CMP
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The formation of a cap layer in semiconductor structures often results in the dishing phenomenon, which causes contact shorts and increases source/drain resistance due to the limitations of existing replacement gate techniques.
Innovation Solution
A method involving the use of a substrate with an interlayer dielectric and recesses filled with metal gates, followed by a cap material layer and multiple sacrifice layers with varying compositions, where a chemical mechanical polishing process removes the sacrifice layers and cap material layer above the interlayer dielectric, preventing dishing by controlling the polishing rates and maintaining a uniform surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a cap layer is formed on top of the replacement metal gate structure, then contact shorts between contact plugs and metal gates are prevented, but dishing phenomenon occurs on the cap layer
Solution Approach 1:
The patent introduces a sacrificial layer as an intermediary material between the cap layer and the metal gate. This sacrificial layer has different etch selectivity compared to the cap layer, allowing it to be selectively removed during chemical mechanical polishing (CMP) to compensate for dishing. The sacrificial layer acts as a mediator that enables the cap layer to maintain both its protective function and surface flatness by providing a buffer that can be differentially removed.
Solution Approach 2:
The patent changes the material composition and thickness parameters of the sacrificial layer to control the CMP process. By adjusting the sacrificial layer's thickness and material properties (etch selectivity), the process compensates for dishing in the cap layer. The parameter changes in the sacrificial layer's removal rate during CMP allow the cap layer surface to be planarized while maintaining the underlying metal gate structure.
2Productivity
If replacement gate techniques are used to substitute metal gate electrodes for polysilicon gate electrodes, then drive current is improved by reducing polysilicon depletion, but dishing phenomenon occurs on the cap layer
Solution Approach 1:
The sacrificial layer serves as an intermediary that enables the replacement gate technique to achieve both high drive current and flat cap layer surface. By positioning the sacrificial layer between the metal gate and cap layer, it allows the metal gate to provide low resistance (high productivity) while the sacrificial layer compensates for dishing during CMP, maintaining surface flatness.
Solution Approach 2:
The gate structure is segmented into multiple functional layers: the metal gate electrode for electrical function, the sacrificial layer for structural compensation, and the cap layer for protection. This segmentation allows each layer to perform its specific function independently - the metal gate provides low resistance for high drive current, while the sacrificial layer provides dishing compensation for surface flatness.
3Reliability
If a cap layer is formed to prevent contact shorts, then contact plug to metal gate shorts are avoided, but dishing phenomenon increases source/drain resistance
Solution Approach 1:
The patent changes the thickness parameter of the sacrificial layer to control the CMP removal rate. By optimizing the sacrificial layer thickness, the CMP process removes the sacrificial material faster than the cap layer, compensating for dishing and maintaining a flat cap layer surface. This prevents the cap layer from becoming too thick in localized areas, which would otherwise increase source/drain resistance while still maintaining contact short prevention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively eliminates the dishing phenomenon, ensuring a flat top surface for the gate cap layer and interlayer dielectric, thereby preventing contact shorts and enhancing the lithography/etching process window.
Implementation Method 1
a chemical mechanical polishing process is preformed to remove the second sacrifice layer, the first sacrifice layer and the cap material layer above a top surface of the interlayer dielectric
Data Source
AI summary
A method of fabricating a gate cap layer includes providing a substrate with an interlayer dielectric disposed thereon, wherein a recess is disposed in the interlayer dielectric and a metal gate fills in a lower portion of the recess. Later, a cap material layer is formed to cover the interlayer dielectric and fill in an upper portion of the recess. After that, a first sacrifice layer and a second sacrifice layer are formed in sequence to cover the cap material layer. The first sacrifice layer has a composition different from a composition of the cap material layer. The second sacrifice layer has a composition the same as the composition of the cap material layer. Next, a chemical mechanical polishing process is preformed to remove the second sacrifice layer, the first sacrifice layer and the cap material layer above a top surface of the interlayer dielectric.