Self-Aligned Gate Cap Etch-Stop Layer Reduces Parasitic Capacitance
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Solution Overview
Problem
As transistor dimensions decrease, the proximity of source and drain metallization contacts to the gate conductor increases gate-to-drain and gate-to-source capacitance, leading to significant load capacitance in semiconductor circuits, which hinders circuit speed and functionality.
Innovation Solution
A self-aligned gate cap structure is implemented, featuring an etch-stop layer between the dielectric oxide and the gate cap, which reduces the leakage between the contact region and the gate, thereby decreasing gate capacitance and providing an additional etch process margin. This structure includes a gate on a substrate, a gate cap surrounding the gate, a self-aligned contact region, and a dielectric oxide on top of the gate, with the etch-stop layer deposited conformally using atomic layer deposition and selectively etched to form a contact trench.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are reduced to increase circuit density, then circuit functionality and integration are improved, but gate-to-drain and gate-to-source capacitance increases due to increased proximity of source and drain contacts to the gate conductor
Solution Approach 1:
The gate cap structure is segmented into multiple layers including a first gate cap layer, a dielectric oxide layer, and a second gate cap layer. This segmentation allows the dielectric oxide layer to be positioned between the contact region and the gate, effectively reducing parasitic capacitance while maintaining the compact structure needed for high circuit density
Solution Approach 2:
A dielectric oxide layer is introduced as an intermediary element between the contact region and the gate conductor. This intermediate layer increases the spacing between the contact via and the gate, thereby reducing gate-to-drain and gate-to-source capacitance without requiring larger overall transistor dimensions
2Manufacturing precision
If contact via is misaligned with respect to the gate, then manufacturing tolerance is improved, but spacing between gate and via becomes significantly less than 40 nanometers, increasing capacitance
Solution Approach 1:
The dielectric oxide layer is deposited in advance between the contact region and the gate structure before final contact formation. This preliminary action ensures that even if misalignment occurs during subsequent manufacturing steps, the additional spacing provided by the dielectric layer prevents excessive capacitance
Solution Approach 2:
The dielectric oxide layer serves as a mediator that decouples the alignment precision requirements from the final capacitance value. By introducing this intermediate layer, the system can tolerate greater misalignment while maintaining acceptable capacitance levels
3Productivity
If spacing between gate and contact via is reduced to increase circuit density, then integration is improved, but gate-to-drain and gate-to-source capacitance increases significantly
Solution Approach 1:
Instead of increasing horizontal spacing between gate and contact via, the solution adds a vertical dimension by inserting the dielectric oxide layer between them. This dimensional change allows maintaining small footprint for high integration while achieving effective capacitance reduction through increased vertical separation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The self-aligned gate cap structure effectively reduces parasitic overlap capacitances, leading to faster, smaller, and more reliable transistors by increasing the space between the contact region and the gate, thus mitigating contact leakage and enhancing circuit speed.
Implementation Method 1
an etch-stop layer deposited conformally using atomic layer deposition
Data Source
AI summary
According to embodiments of the present invention, a method of forming a self-aligned contact includes depositing an etch-stop liner on a surface of a gate cap and a contact region. A dielectric oxide layer is deposited onto the etch-stop layer. The dielectric oxide layer and the etch-stop liner are removed in a region above the contact region to form a removed region. A contact is deposited in the etched region.