Gate Capping Layer Protection During MOL Contact Etching
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Solution Overview
Problem
The fabrication of conductive contacts in integrated circuits during middle-of-the-line (MOL) interconnect formation can degrade the gate capping layer, leading to increased parasitic capacitance and reduced structural integrity due to etching processes that use fluorine-based etchants, causing damage to the gate capping layer and rounding of its corners.
Innovation Solution
A selective etch and deposition process is employed to form a dielectric protection layer along the upper surface of the gate capping layer while etching the lower inter-level dielectric (ILD) layer, preventing damage to the gate capping layer and maintaining its structural integrity by reducing the formation of volatile by-products and rounding of corners.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If fluorine-based etchants are used to form contact openings in the lower ILD layer, then contact openings can be effectively etched, but the gate capping layer thickness is reduced and corners are rounded, leading to increased parasitic capacitance and leakage current
Solution Approach 1:
A dielectric protection layer is deposited over the gate capping layer before etching the lower ILD layer. This protection layer acts as an intermediary that prevents the fluorine-based etchant from directly contacting and damaging the gate capping layer, thereby maintaining its thickness and corner sharpness while still allowing contact openings to be formed in the lower ILD layer
Solution Approach 2:
The dielectric protection layer is applied in advance before the etching process to preemptively protect the gate capping layer from the harmful effects of fluorine-based etchants. This preliminary protective action prevents thickness reduction and corner rounding before they can occur
2Ease of manufacture
If the gate capping layer is exposed to fluorine-based etchants during contact formation, then contact openings can be formed, but parasitic capacitance between adjacent contacts increases
Solution Approach 1:
The dielectric protection layer serves as a mediator that isolates the gate capping layer from the etchant, preventing the formation of volatile by-products and maintaining the electrical properties of the gate capping layer, thereby reducing parasitic capacitance between adjacent contacts
3Productivity
If conventional etching processes are used without protection, then the process is simple and fast, but the gate capping layer suffers from thickness reduction and corner rounding
Solution Approach 1:
The dielectric protection layer is deposited in advance before the etching process begins. This preliminary action ensures that when the high-speed etching process occurs, the gate capping layer is already protected, allowing fast processing without sacrificing dimensional precision
Solution Approach 2:
The protection layer enables the use of aggressive, fast-etching fluorine-based chemistry by interposing a protective barrier between the etchant and the gate capping layer, thus maintaining both high productivity and manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance and enhances the structural integrity and performance of the integrated chip by preventing damage to the gate capping layer during the formation of conductive contacts, thereby improving device reliability and performance.
Implementation Method 1
A selective etch and deposition process is performed to form a dielectric protection layer on the gate capping layer
Implementation Method 2
concurrently etching the lower ILD layer to form contact openings
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated chip including a gate electrode over a substrate. A pair of source/drain regions are disposed in the substrate on opposing sides of the gate electrode. A dielectric layer is over the substrate. An etch stop layer is between the gate electrode and the dielectric layer. A gate capping layer overlies the gate electrode, continuously extends from a top surface of the etch stop layer to a top surface of the gate electrode, and comprises a curved sidewall over the top surface of the etch stop layer. A conductive contact overlies an individual source/drain region. A width of the conductive contact continuously decreases from a top surface of the conductive contact to a first point disposed above a lower surface of the gate capping layer. The conductive contact extends along the curved sidewall of the gate capping layer.