Gate Cap Removal Using Sacrificial Polish Layer
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Solution Overview
Problem
The existing methods for removing gate cap materials in semiconductor fabrication often damage the substrate and sidewall spacers, leading to unacceptable shifts in threshold voltage and increased yield loss, particularly during reactive ion etching processes used for polysilicon gate structures.
Innovation Solution
A method involving the formation of a gate electrode structure with a gate insulation layer, sidewall spacers, and a gate cap layer, followed by the deposition of an etch stop layer and a spacer material, and subsequent planarization processes using a sacrificial polish layer to protect the active area during cap removal, ensuring minimal damage to the substrate and spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If reactive ion etching is used to remove gate cap materials, then the gate cap removal is effective, but the substrate and sidewall spacers are damaged
Solution Approach 1:
A sacrificial polish layer is deposited over the gate cap layer before etching. This preliminary action creates a protective barrier that prevents the reactive ion etching process from directly attacking the substrate and sidewall spacers, thereby maintaining their integrity while still allowing effective gate cap removal
Solution Approach 2:
The sacrificial polish layer acts as an intermediary between the reactive ion etching process and the underlying substrate/sidewall spacer structures. It absorbs the harmful effects of the etching process, protecting the critical components while enabling the gate cap removal to proceed effectively
2Productivity
If reactive ion etching is used to remove gate cap materials, then the gate cap is removed, but threshold voltage shifts occur
Solution Approach 1:
The sacrificial polish layer is deposited in advance to protect the substrate and sidewall spacers during etching. By preventing damage to these structures, the process maintains consistent electrical characteristics and prevents unwanted threshold voltage shifts
Solution Approach 2:
The sacrificial polish layer, which is removed after serving its protective function, converts the potentially harmful reactive ion etching process into a beneficial one. The layer absorbs the harmful effects, allowing the etching to proceed effectively on the gate cap while protecting the underlying structures that determine device electrical characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces damage to the substrate and sidewall spacers, maintaining the integrity of the gate electrode structure and preventing excessive erosion, thereby improving the consistency and reliability of the semiconductor device fabrication process.
Implementation Method 1
performing at least one first planarization process to remove the portion of said layer of spacer material positioned above the gate electrode, the portion of said etch stop layer positioned above the gate electrode and the gate cap layer
Data Source
AI summary
Disclosed herein is a method of forming a semiconductor device. In one example, the method includes forming a gate electrode structure above a semiconducting substrate, wherein the gate electrode structure includes a gate insulation layer, a gate electrode, a first sidewall spacer positioned proximate the gate electrode, and a gate cap layer, and forming an etch stop layer above the gate cap layer and above the substrate proximate the gate electrode structure. The method further includes forming a layer of spacer material above the etch stop layer, and performing at least one first planarization process to remove the portion of said layer of spacer material positioned above the gate electrode, the portion of the etch stop layer positioned above the gate electrode and the gate cap layer.