Low-Resistance Gate Capping Layer for FinFET Signal Delay
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Solution Overview
Problem
As semiconductor devices are scaled down, gate resistance increases, leading to slower device speeds, particularly for devices located far away from the gate via, due to longer signal paths and increased time constants.
Innovation Solution
A low-resistance capping layer, such as a tungsten-containing layer, is implemented over the gate electrode of FinFET and GAA devices, reducing gate resistance by providing a lower resistivity path for electrical signals, even for devices at the end of the active region structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down to increase functional density, then production efficiency and cost are improved, but gate resistance increases leading to slower device speeds
Solution Approach 1:
The patent applies local quality by forming a low-resistance capping layer selectively over the gate electrode structure. This capping layer is deposited only in specific regions where resistance reduction is needed, particularly over the gate electrode but not necessarily over all surrounding structures. The selective application of this low-resistance material locally improves electrical conductivity where it is most needed, resolving the contradiction between scaled-down dimensions and acceptable gate resistance levels.
Solution Approach 2:
The patent employs composite materials by combining the existing gate electrode material with an additional low-resistance capping layer. This creates a composite gate structure where the capping layer (such as tungsten or copper) provides superior electrical conductivity while the underlying gate electrode material maintains its functional properties. This composite approach allows the device to achieve both small dimensions and low gate resistance by leveraging the complementary properties of different materials.
2Manufacturing precision
If gate electrode dimensions are reduced to enable smaller device geometry, then manufacturing precision is improved, but gate resistance increases due to longer signal paths
Solution Approach 1:
The patent applies parameter changes by modifying the electrical resistance parameter of the gate electrode through the addition of a low-resistance capping layer. While the physical dimensions of the gate electrode are reduced for scaling, the electrical properties are improved by introducing material with lower resistivity. This change in material parameter compensates for the increased resistance that would otherwise result from smaller dimensions and longer signal paths.
Solution Approach 2:
The low-resistance capping layer serves as an intermediary between the gate via and the active region structures. It provides a low-resistance pathway for electrical signals to travel from the gate via through the gate electrode to the active regions, mediating the electrical connection and reducing the overall gate resistance despite the reduced gate electrode dimensions.
3Area of stationary object
If devices are located far away from gate via to increase functional density, then area utilization is improved, but signal loss increases due to increased time constants
Solution Approach 1:
The patent applies local quality by providing enhanced electrical conductivity specifically in the gate electrode structure through the capping layer. This local improvement in conductivity compensates for the increased distance signals must travel to reach devices located far from the gate via, reducing signal loss and time constants despite the larger signal paths required for high area utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The low-resistance capping layer significantly reduces gate resistance and signal loss, resulting in faster device speeds and improved performance for semiconductor devices, especially those farthest from the gate via.
Implementation Method 1
A low-resistance capping layer, such as a tungsten-containing layer, is implemented over the gate electrode of FinFET and GAA devices, reducing gate resistance by providing a lower resistivity path for electrical signals
Data Source
AI summary
A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.