Stacked Semiconductor Gate Capping for Scaled MOSFET Reliability
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Solution Overview
Problem
The scale-down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improvements in electrical and reliability characteristics.
Innovation Solution
A semiconductor device design featuring vertically stacked semiconductor patterns with specific gate and spacer configurations, including a gate capping pattern in contact with a gate spacer, and active contacts with defined spacing to enhance structural integrity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to reduce pattern size and design rule, then device integration density is improved, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar MOS-FET structure to a three-dimensional stacked semiconductor pattern configuration. Multiple semiconductor patterns are vertically stacked to form a channel pattern, enabling the device to maintain operational performance while reducing footprint area. This dimensional change allows continued scaling without the operational degradation that plagues conventional planar transistors at small dimensions.
Solution Approach 2:
The gate electrode is divided into multiple segments: inner gate electrodes positioned between adjacent semiconductor patterns and outer gate electrodes on the uppermost semiconductor patterns. This segmented gate structure provides independent control over different regions of the stacked channel, improving electrical characteristics and enabling better performance at scaled dimensions.
2Reliability
If vertically stacked semiconductor patterns are implemented to maintain performance at scaled dimensions, then operational properties are improved, but device complexity increases
Solution Approach 1:
Multiple semiconductor patterns are vertically stacked and merged to form a unified channel pattern. The inner gate electrodes and outer gate electrodes are combined to create an integrated gate structure that controls the stacked channel. This merging approach manages complexity by creating cohesive structures from multiple components rather than treating them as separate elements.
Solution Approach 2:
The stacked semiconductor patterns serve multiple functions: they form the channel region, provide pathways for carrier transport, and enable independent gate control. The gate spacers simultaneously provide electrical isolation and structural support. This multi-functionality reduces the need for additional dedicated components, managing overall device complexity.
3Reliability
If gate spacers and gate capping patterns are added to enhance structural integrity, then reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
Gate spacers are formed on the side surfaces of the gate electrode stack before subsequent processing steps. The gate capping pattern is deposited on the outer gate electrodes in advance to protect the gate structure during manufacturing. These preliminary actions ensure structural integrity is established early, preventing damage in later steps and reducing the need for high-precision alignment in subsequent operations.
Solution Approach 2:
The gate capping pattern acts as a protective layer that cushions the gate electrode structure from mechanical stress and damage during manufacturing processes. The gate spacers provide structural support and isolation that prevent unintended interactions between adjacent structures. This beforehand cushioning protects the complex gate structure, reducing the stringency of manufacturing precision requirements.
Data Source
AI summary
A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern comprising semiconductor patterns, which are vertically stacked and are spaced apart from each other in a vertical direction, a source/drain pattern connected to the channel pattern, an inner gate electrode interposed between adjacent ones of the semiconductor patterns, an outer gate electrode on an uppermost one of the semiconductor patterns, a gate spacer on a side surface of the outer gate electrode, and a gate capping pattern on a top surface of the outer gate electrode. The gate capping pattern is in contact with a top surface of the gate spacer.