Gate Structure Parasitic Capacitance Reduction
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Solution Overview
Problem
High-k metal oxide semiconductor field effect transistors (MOSFETs) face performance issues due to significant parasitic capacitance between the gate electrode and source/drain regions caused by high-k gate dielectric material on the sidewalls of the U-shaped recessed region in the replacement gate process, which increases resistance and impacts performance.
Innovation Solution
A method is developed to form a gate structure with reduced parasitic capacitance by depositing a high-k gate dielectric layer and a metal cap layer within a gate cavity, followed by ion implantation into the sacrificial cap layer to damage and remove vertical portions, exposing the metal cap and high-k gate dielectric layers, thereby limiting the vertical extent of the gate components and reducing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-k gate dielectric material is deposited on the sidewalls of the U-shaped recessed region to form the gate stack, then the gate electrode can be formed after high temperature processing steps with minimal damage, but significant parasitic capacitance is introduced between the gate electrode and source/drain regions
Solution Approach 1:
The patent removes the high-k gate dielectric material from the sidewalls of the U-shaped recessed region, extracting only the harmful parasitic capacitance effect while preserving the gate stack formation benefits. This is achieved by selectively etching or removing the sidewall dielectric after deposition, leaving the gate electrode intact for post-deposition formation.
Solution Approach 2:
The patent applies different treatments to different regions of the gate dielectric structure. The bottom surface of the recessed region retains the high-k gate dielectric for proper gate function, while the sidewalls are cleared of dielectric material to eliminate parasitic capacitance. This local differentiation resolves the contradiction between maintaining gate integrity and reducing parasitic effects.
2Reliability
If work function metal portion is added to the gate electrode to adjust threshold voltage, then threshold voltage control is achieved, but the resistance of the gate electrode increases due to vertical portions surrounding other conductive material
Solution Approach 1:
The patent configures the work function metal portion with a specific geometry where only the horizontal portion contacts the high-k gate dielectric for threshold voltage adjustment, while vertical portions are minimized or eliminated to reduce resistive losses. This local optimization allows threshold control without excessive resistance penalty.
Solution Approach 2:
The patent designs the gate electrode structure in advance with optimized work function metal geometry that prevents excessive resistance buildup. By pre-planning the horizontal versus vertical portion configuration, the design achieves both threshold voltage control and acceptable resistance levels before fabrication completes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces gate-contact parasitic capacitance, enhancing the performance of the MOSFET by minimizing resistance and improving the structure's efficiency.
Implementation Method 1
After ion implantation into vertical portions of the sacrificial cap layer, at least part of the vertical portions of the material stack can be removed
Data Source
AI summary
The present disclosure provides a method of forming a gate structure of a semiconductor device with reduced gate-contact parasitic capacitance. In a replacement gate scheme, a high-k gate dielectric layer is deposited on a bottom surface and sidewalls of a gate cavity. A metal cap layer and a sacrificial cap layer are deposited sequentially over the high-k gate dielectric layer to form a material stack. After ion implantation in vertical portions of the sacrificial cap layer, at least part of the vertical portions of the material stack is removed. The subsequent removal of a remaining portion of the sacrificial cap layer provides a gate component structure. The vertical portions of the gate component structure do not extend to a top of the gate cavity, thereby significantly reducing gate-contact parasitic capacitance.