Gate Electrode Capping Layer for Etch-Resistant Contact Formation
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Solution Overview
Problem
The process of forming self-aligned source/drain contacts in transistors can damage gate structures due to etching, leading to gate spacer loss and corner rounding, which results in performance degradation, especially in tight pitch geometries and high aspect ratios, and existing silicon nitride protective layers fail to mitigate these issues.
Innovation Solution
A hard mask layer resistant to etching chemistry is used, comprising materials like metal-oxides, metal-silicates, metal-aluminates, or metal-nitrides with transition or rare earth metals, which can be deposited in a crystalline, amorphous, or laminated form to protect the gate structures during the formation of source/drain contact openings, minimizing gate spacer loss and corner rounding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If etching operations are performed to form self-aligned source/drain contacts, then contact formation is achieved, but gate structure damage occurs due to physical ion bombardment
Solution Approach 1:
A capping layer is introduced as an intermediary protective barrier between the etching environment and the gate structure. This layer absorbs the harmful physical ion bombardment during etching operations, preventing direct damage to the gate while allowing the etching process to proceed effectively for contact formation.
Solution Approach 2:
The capping layer is deposited onto the gate structure before the etching operations begin. This preliminary protective action ensures that the gate is shielded from damage before exposure to the harmful etching environment, enabling subsequent contact formation without gate degradation.
2Reliability
If over polishing is performed to remove damaged gate portions, then gate integrity is restored, but gate height loss occurs and transistor performance degrades
Solution Approach 1:
The capping layer converts the harmful effect of being removed during polishing into a benefit. By intentionally designing the capping layer to be removed during polishing, the damaged portions of the gate are simultaneously removed, restoring gate integrity while the capping layer's presence during etching prevented the damage in the first place.
Solution Approach 2:
The polishing process parameters are optimized to control the removal rate. By carefully controlling polishing conditions, the process removes damaged gate portions and the capping layer while limiting gate height loss to less than 20 nm, maintaining manufacturing precision while restoring gate integrity.
3Object-affected harmful factors
If existing silicon nitride protective layers are used during etching, then some protection is provided, but gate spacer loss and corner rounding still occur
Solution Approach 1:
The protective structure uses a composite approach by depositing a capping layer with specific material properties onto the gate structure. This capping layer material is selected to provide superior resistance to the specific etching chemistry being used, offering better protection than silicon nitride alone against both gate spacer loss and corner rounding.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of the hard mask layer significantly reduces gate height loss and corner rounding, allowing for a more controlled polishing process, thereby maintaining transistor performance and reducing gate height loss to less than 20 nm.
Implementation Method 1
A hard mask layer resistant to etching chemistry is used, comprising materials like metal-oxides, metal-silicates, metal-aluminates, or metal-nitrides
Implementation Method 2
which can be deposited in a crystalline, amorphous, or laminated form to protect the gate structures
Data Source
AI summary
The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.