Gate Capping Layer for Etch-Resistant Self-Aligned Contacts
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Solution Overview
Problem
The process of forming self-aligned source/drain contacts in transistors often results in gate spacer loss and top corner rounding due to low etching selectivity, leading to electrical shorts and performance degradation, especially in tight pitch geometries and high aspect ratios, where existing integration schemes like silicon nitride protective layers fail to prevent these issues.
Innovation Solution
A hard mask layer resistant to etching chemistry is used, comprising materials like metal-oxides, metal-silicates, metal-aluminates, or metal-nitrides with transition or rare earth metals, which can be deposited in a crystalline, amorphous, or laminate microstructure to protect the gate structures during the formation of source/drain contact openings, minimizing gate spacer loss and corner rounding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon nitride protective layers are used, then gate protection is provided, but gate spacer loss and corner rounding still occur due to low etching selectivity
Solution Approach 1:
The patent uses a composite capping layer structure comprising multiple materials (e.g., tungsten, tantalum, titanium, molybdenum, or their oxides/nitrides) deposited in sequence. This composite structure provides superior etching resistance compared to single-material protective layers like silicon nitride, while maintaining gate protection and preventing spacer loss through the combined properties of different materials with varying etching selectivities.
Solution Approach 2:
The patent changes the material composition and structural parameters of the capping layer by selecting from multiple metal options and their different oxidation states (metal, oxide, nitride forms). This parameter optimization enables the capping layer to achieve high etching selectivity and resistance, directly addressing the insufficient protection provided by conventional silicon nitride layers.
2Manufacturing precision
If over polishing is performed to remove damaged gate portions, then gate damage is removed, but gate height loss and transistor performance degradation occur
Solution Approach 1:
The capping layer is deposited on the gate structure before the etching process that forms source/drain contacts. This preliminary protective action prevents physical ion bombardment damage to the gate top portions during etching, eliminating the need for subsequent over-polishing operations that would cause gate height loss and performance degradation.
Solution Approach 2:
The capping layer acts as a cushioning protective barrier deposited beforehand on the gate structure. This layer absorbs and resists the physical ion bombardment during etching, preventing direct damage to the gate material and eliminating the need for corrective over-polishing that would compromise gate height and transistor performance.
3Productivity
If tight pitch geometries and high aspect ratios are used, then transistor density is improved, but gate spacer loss and electrical shorts increase
Solution Approach 1:
The patent employs composite capping layer materials with high etching selectivity to maintain precise gate dimensions in tight pitch geometries. This composite structure prevents gate spacer loss and corner rounding even when manufacturing high-density devices with small feature sizes, thereby preventing electrical shorts while achieving high transistor density.
Solution Approach 2:
The capping layer provides localized protective quality specifically at the gate top portions and corners where damage is most critical. This localized protection maintains the integrity of gate spacers and prevents corner rounding in tight pitch geometries, ensuring electrical isolation is maintained while achieving high device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces gate height loss to less than 20 nm and prevents electrical shorts by maintaining the integrity of the gate structures during the etching process, enhancing transistor performance and reliability.
Implementation Method 1
A hard mask layer resistant to etching chemistry is used, comprising materials like metal-oxides, metal-silicates, metal-aluminates, or metal-nitrides
Implementation Method 2
which can be deposited in a crystalline, amorphous, or laminate microstructure to protect the gate structures
Data Source
AI summary
The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.