Gate Capping Structure for FinFET Etch Protection
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Solution Overview
Problem
The semiconductor industry faces challenges in protecting the structural integrity of insulating layers during the formation of self-aligned source/drain contact structures in finFETs, leading to potential electrical shorting between gate and source/drain contact structures due to the complexity of etching narrow regions in finFET manufacturing processes.
Innovation Solution
The implementation of gate capping structures that provide a larger protection area, acting as etch stop layers and preventing the etching of insulating layers, thereby maintaining the structural integrity of gate structures and preventing electrical shorting during the formation of source/drain contact structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching processes are used to form self-aligned source/drain contact structures in finFETs, then the manufacturing process can proceed, but the insulating layers lose structural integrity leading to electrical shorting between gate and source/drain contact structures
Solution Approach 1:
The gate capping structure is formed in advance before the etching process that creates source/drain contact structures. This preliminary protective layer is deposited over the gate structure and insulating layers, providing pre-protection against the subsequent etching operations. The capping structure remains in place during the etching process to prevent damage to the insulating layers, and is removed only after the etching is complete.
Solution Approach 2:
The gate capping structure serves as an intermediary protective element between the etching process and the insulating layers. This intermediate layer absorbs the mechanical stress and chemical exposure of the etching process, preventing direct contact between the etchant and the vulnerable insulating layers. The capping structure acts as a buffer that protects the underlying structures while allowing the etching process to proceed.
2Reliability
If the gate structure is protected during etching, then electrical shorting is prevented, but the device complexity increases due to additional gate capping structures
Solution Approach 1:
The gate capping structure performs multiple functions: it protects the insulating layers during etching, serves as an etch stop layer to control etching depth, and maintains the structural integrity of the gate region throughout the fabrication process. By consolidating these protective and control functions into a single structure, the patent avoids the need for multiple separate protective layers, thereby reducing overall device complexity while maintaining reliability.
Solution Approach 2:
The gate capping structure is a temporary protective element that is discarded after serving its protective function. It is deposited before the etching process, performs its protective duty during etching, and is then removed in a subsequent cleaning step. This temporary nature allows the structure to be optimized solely for protection without permanent complexity, as it is recovered (removed) after use.
3Reliability
If the protection area of gate capping structures is increased, then etching protection is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The gate capping structure is formed using a self-aligned process where the capping material is deposited conformally over the gate structure and then planarized. The gate structure itself serves as the alignment reference for the capping structure, eliminating the need for separate alignment steps. This self-service approach ensures that the capping structure automatically aligns with the gate, reducing manufacturing precision requirements while providing extended protection area.
Solution Approach 2:
The patent optimizes the lateral dimensions of the gate capping structure to extend beyond the gate edges, creating an overlapping protection zone. By changing the dimensional parameters of the capping structure (making it wider than the gate), the protection area is increased without requiring higher alignment precision, as the extended margins provide a buffer zone that tolerates alignment variations.
Data Source
AI summary
A method of forming a semiconductor device includes forming a source/drain region and spacers on a substrate. The method further includes forming an etch stop layer on the spacers and the source/drain region and forming a gate structure between the spacers. The method further includes etching back the gate structure, etching back the spacers and the etch back layer, and forming a gate capping structure on the etched back gate structure, spacers, and etch stop layer.