Fin Transistor Gate Capping Pattern Impurity Doping
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Solution Overview
Problem
Semiconductor devices face challenges in achieving high integration density, reliability, and multifunctionality due to limitations in their design and fabrication processes, particularly in the fin-type transistor structure.
Innovation Solution
The semiconductor devices incorporate a substrate with a device isolation layer, active fins, a gate structure with a capping pattern doped with impurities, and spacers with varying impurity concentrations, along with source/drain contacts, to enhance electrical characteristics and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fin-type transistor structure is used to achieve high integration density, then the number of devices per unit area increases, but the reliability and electrical characteristics deteriorate due to fabrication limitations and structural complexity
Solution Approach 1:
The patent applies local quality by introducing a capping pattern with non-uniform impurity concentration distribution. The capping pattern has a first region with higher impurity concentration and a second region with lower impurity concentration, allowing different portions of the gate structure to have optimized electrical characteristics for their specific functional requirements, thereby improving reliability while maintaining high integration density
Solution Approach 2:
The patent changes the impurity concentration parameter within the capping pattern to optimize device performance. By varying the impurity concentration from the first region to the second region, the patent adjusts electrical characteristics such as carrier mobility and threshold voltage, resolving the contradiction between integration density and reliability
2Ease of manufacture
If the gate structure is simplified for ease of manufacture, then fabrication complexity decreases, but electrical characteristics and reliability deteriorate
Solution Approach 1:
The gate structure is segmented into multiple components: gate electrode, capping pattern, and spacer. The capping pattern is further divided into a first region and a second region with different impurity concentrations. This segmentation allows each component to be optimized independently for its specific function while maintaining overall fabrication simplicity
Solution Approach 2:
The capping pattern is formed with predetermined impurity concentration distribution before final device assembly. This preliminary action of doping the capping pattern with specific impurity concentrations in different regions prepares the gate structure with optimized electrical characteristics in advance, ensuring reliability without complicating the manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the electrical characteristics and reliability of semiconductor devices by optimizing the fin-type transistor structure, enabling higher integration density and multifunctionality.
Implementation Method 1
The capping pattern may include a first part and a second part between the first part and the gate pattern. The first and second parts may have impurity concentrations different from each other.
Implementation Method 2
The spacer may include impurities doped therein. The spacer may comprise a first spacer segment between the gate pattern and the source/drain contact, and a second spacer segment between the capping pattern and the source/drain contact. The first and second spacer segments may have impurity concentrations different from each other.
Data Source
AI summary
Semiconductor devices and methods of forming the semiconductor devices are provided. The semiconductor devices may include a substrate, a device isolation layer that defines an active region, an active fin vertically protruding from the active region of the substrate and extending in a horizontal direction, a gate structure traversing the active fin, and a source/drain contact on the active fin on a side of the gate structure. The gate structure may include a gate pattern and a capping pattern on the gate pattern, and the capping pattern may have impurities doped therein. The capping pattern may include a first part and a second part between the first part and the gate pattern. The first and second parts may have impurity concentrations different from each other.