Gate Capping Pattern with Extended Sidewall Portions
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high reliability, performance, and integration density, particularly in field effect transistors, due to limitations in gate electrode protection and contact plug formation processes.
Innovation Solution
The semiconductor device incorporates a gate capping pattern with extended portions covering both sidewalls of the gate electrode, which is wider than the gate electrode, and includes a gate capping insulating layer formed using atomic layer deposition, providing protection against etch damage and enabling self-aligned contact plug formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate electrode structure is used without extended capping portions, then the device structure is simpler and manufacturing is easier, but the gate electrode is vulnerable to etch damage during contact plug formation and process margin is reduced
Solution Approach 1:
The gate capping pattern is formed with extended portions that protrude over the contact region before contact hole etching begins. This preliminary configuration of the capping layer creates a protective overlay that prevents etch damage to the gate electrode during subsequent processing steps, eliminating the need for additional protective measures.
Solution Approach 2:
The extended portions of the gate capping pattern serve as an intermediary protective layer between the etch process and the gate electrode. This intermediate structure absorbs the harmful etch exposure, preventing direct contact between the etch chemistry and the gate electrode, thereby protecting the gate while allowing the etch to proceed for contact hole formation.
2Reliability
If the gate capping pattern width is increased to cover sidewalls, then protection against etch damage is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The gate capping pattern is formed using a self-aligned process where the extended portions automatically align with the gate electrode structure. The capping layer is deposited conformally and then patterned such that the extended portions naturally overhang the contact region, eliminating the need for separate alignment steps and reducing manufacturing precision requirements despite the increased width.
Solution Approach 2:
The gate capping pattern extends in the lateral dimension beyond the gate electrode width, creating an overhang structure. This dimensional extension provides protective coverage over the contact region without requiring precise vertical alignment, as the protection is achieved through lateral overlap rather than vertical positioning precision.
3Manufacturing precision
If self-aligned contact plug formation is enabled through extended capping portions, then process margin is increased, but the device structure becomes more complex
Solution Approach 1:
The extended portions of the gate capping pattern serve as self-aligned masks for contact hole etching. The etch process uses the extended capping portions as the defining boundary, automatically positioning contact holes with high precision relative to the gate electrode without requiring additional alignment marks or complex masking steps, thereby increasing process margin.
Solution Approach 2:
The gate capping pattern performs multiple functions: it provides electrical connection, protects the gate electrode, and serves as a self-aligned mask for contact hole formation. This multi-functionality is achieved through the extended portions configuration, which enables contact plug alignment while maintaining the other functions, reducing the need for separate specialized structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the electric characteristics of the semiconductor device by protecting the gate electrodes during contact plug formation, increasing the process margin and ensuring improved reliability and performance.
Implementation Method 1
which is wider than the gate electrode, and includes a gate capping insulating layer formed using atomic layer deposition
Data Source
AI summary
Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, and a gate capping pattern on the gate electrode. The gate capping pattern may have a width larger than that of the gate electrode, and the gate capping pattern may include extended portions extending toward the substrate and at least partially covering both sidewalls of the gate electrode.